I²C Pull-Up Resistor Calculator
I²C Pull-Up Resistor Calculator
The window your I²C pull-ups have to sit in: the minimum set by the sink current and Vₒₗ, the maximum set by the rise time your speed mode allows for the bus capacitance you have, a standard value between them, and the rise time and sink current it actually gives — all from NXP UM10204.
I²C pull-up resistor
a Fast-mode (400 kHz) bus at 3.3 V with 150 pF of bus capacitance, Vₒₗ 0.4 V, E24 values
The two limits on Rₚ
- Vₒₗ
- the low level the driving device is allowed to sit at while sinking Iₒₗ; 0.4 V in the standard
- Iₒₗ
- 3 mA in Standard- and Fast-mode, 20 mA in Fast-mode Plus
- tᵣ
- 1000 ns, 300 ns and 120 ns for the three modes
- 0.8473
- the rising edge is an RC charge and the spec measures it between 0.3 Vᴅᴅ and 0.7 Vᴅᴅ, so the constant is ln((1−0.3) ÷ (1−0.7)) = ln(7/3)
Worked example
a Fast-mode (400 kHz) bus at 3.3 V with 150 pF of bus capacitance, Vₒₗ 0.4 V, E24 values
Minimum: (Vᴅᴅ − Vₒₗ) ÷ Iₒₗ = (3.3 − 0.4) ÷ 3 mA = 966.7 Ω
Maximum: tᵣ ÷ (0.8473 × Cᵇ) = 300 ns ÷ (0.8473 × 150 pF) = 2.36 kΩ
The geometric middle of that window is 1.511 kΩ, and the nearest E24 value is 1.5 kΩ
That gives a rise time of 0.8473 × 1.5 kΩ × 150 pF = 190.6 ns, 63.5% of the 300 ns allowed
and the device holding the line low sinks 1.933 mA, well inside the 3 mA the standard assumes
What UM10204 actually specifies
| Standard-mode | Fast-mode | Fast-mode Plus | |
|---|---|---|---|
| Maximum clock | 100 kHz | 400 kHz | 1 MHz |
| Maximum rise time tᵣ | 1000 ns | 300 ns | 120 ns |
| Sink current Iₒₗ at Vₒₗ = 0.4 V | 3 mA | 3 mA | 20 mA |
| Maximum bus capacitance Cᵇ | 400 pF | 400 pF | 550 pF |
| Rₚ(min) at 3.3 V | 967 Ω | 967 Ω | 145 Ω |
| Rₚ(max) at the maximum Cᵇ | 2,951 Ω | 885 Ω | 258 Ω |
Sizing an I²C pull-up
I²C lines are open-drain: a device can pull the line down but nothing drives it up, so a resistor to Vᴅᴅ does that job. Its value is bounded from both sides and the usable range can be narrow. The lower bound is a DC one — while the line is low, the pull-up pushes (Vᴅᴅ − Vₒₗ) ÷ Rₚ into the device holding it down, and that device is only guaranteed to hold 0.4 V while sinking its rated current. The upper bound is dynamic: releasing the line just leaves Rₚ charging the bus capacitance, and the standard sets how long that edge may take.
Where 0.8473 comes from. It is not a magic number and it is worth deriving rather than copying. The rising edge is a plain RC charge towards Vᴅᴅ, and UM10204 sets the input reference levels at 0.3 Vᴅᴅ and 0.7 Vᴅᴅ, so the specified rise time is the time between those two points. Solve v(t) = Vᴅᴅ(1 − e^−t/RC) at each and subtract: tᵣ = RC·ln((1 − 0.3) ÷ (1 − 0.7)) = RC·ln(7/3) = 0.847298·RC. The standard prints 0.8473, which is that number rounded, and this page uses the logarithm itself.
Too many devices on too long a bus. Bus capacitance is the thing that actually kills an I²C design. Every device pin adds roughly 10 pF, a PCB track adds about half a picofarad per centimetre, and ribbon cable or a backplane adds far more. The standard caps it at 400 pF for Standard- and Fast-mode and 550 pF for Fast-mode Plus, and once you are near the cap the maximum resistor falls until it collides with the minimum and no value works at all. The symptoms are not subtle: rounded rising edges, and then devices reading a logic 1 late, mis-sampling, and acknowledgements that go missing under temperature. The fixes are to shorten the bus, split it with an I²C buffer or repeater, use a bus accelerator that briefly drives the edge, or slow the clock. Adding a smaller resistor only works until the weakest device on the bus can no longer pull the line down to 0.4 V — check the Iₒₗ of every part, not just the microcontroller, and enter the smallest one above.
Practical values. On a short 3.3 V board with a handful of devices, 4.7 kΩ is the traditional answer and is usually fine at 100 kHz; at 400 kHz with any real length on the bus it is often too big, and 2.2 kΩ or 1.5 kΩ is the honest choice. SDA and SCL each need their own resistor. The static current matters on a battery design: a 1.5 kΩ pull-up at 3.3 V costs about 2 mA whenever a line is held low, and both lines idle high between transfers, so the average depends on the traffic — the battery life calculator turns that into runtime. For the timing of the clock itself see the PWM duty cycle calculator, and for the RC charge in general the RC time constant calculator.
Frequently asked questions
What value pull-up resistor should I use for I2C?
Anything between (Vᴅᴅ − 0.4 V) ÷ Iₒₗ and tᵣ ÷ (0.8473 × Cᵇ). On a 3.3 V Fast-mode bus with 150 pF that is 967 Ω to 2.36 kΩ, so 1.5 kΩ. The familiar 4.7 kΩ is outside that window.
Why is there a maximum pull-up value?
Because the rising edge is only an RC charge. The standard allows 1000 ns in Standard-mode, 300 ns in Fast-mode and 120 ns in Fast-mode Plus, and Rₚ × Cᵇ × 0.8473 has to fit inside that.
Where does the 0.8473 constant come from?
It is ln(0.7 ÷ 0.3) = 0.847298. The spec measures the rise between 0.3 Vᴅᴅ and 0.7 Vᴅᴅ, and for an RC charging towards Vᴅᴅ that interval is RC × ln((1−0.3)÷(1−0.7)).
How much bus capacitance do I really have?
Roughly 10 pF per device pin, about 0.5–1 pF per centimetre of PCB track, and much more for ribbon cable or a connector. Ten devices on a 20 cm bus is already well over 100 pF.
My I2C bus is too long and stops working. What do I do?
Reduce the capacitance, not the resistance — below the minimum value the devices can no longer pull the line to 0.4 V. Split the bus with a buffer or repeater, shorten it, or drop to a slower mode.
Related calculators
References
- NXP Semiconductors. UM10204: I²C-bus specification and user manual, Rev. 7.0, 1 October 2021. Input reference levels of 0.3 Vᴅᴅ and 0.7 Vᴅᴅ; Vₒₗ 0.4 V at 3 mA (Standard- and Fast-mode) and at 20 mA (Fast-mode Plus); maximum rise times 1000 ns, 300 ns and 120 ns; maximum bus capacitance 400 pF and 550 pF; Rₚ(max) = tᵣ ÷ (0.8473 · Cᵇ).
- Infineon. Frequently asked questions about I²C lines, developer community knowledge base. Rₚ(max) = tᵣ ÷ (0.8473 × Cᵇ) and Rₚ(min) = (Vᴅᴅ − Vₒₗ(max)) ÷ Iₒₗ, with the 3 mA and 20 mA sink-current figures.
- Horowitz P, Hill W. The Art of Electronics, 3rd ed. Cambridge University Press, 2015. Chapter 14: open-drain buses, wired-AND logic and pull-up sizing.