Buck Converter Design Calculator (CCM/DCM)

Buck Converter Design Calculator (CCM / DCM)

Topology: Non‑isolated Buck

Inputs

Worst case low line
0.85–0.95 typical
20–40% common
Ignored for D calc; used for stress approx
Capacitive portion

Key Results

Component Sizing & Stresses

Notes: Uses worst‑case ripple at VIN_max for inductor sizing (buck ripple increases with VIN). Reports duty at VIN_min and VIN_max. Assumes CCM for core equations; calculator flags possible DCM if IL,val ≤ 0. Thermal, losses, and loop design are out of scope. Validate with hardware.

How to Use the Buck Converter Design Calculator

A concise, engineer‑friendly guide for sizing the inductor, MOSFETs/diode, and capacitors in a non‑isolated buck. Written to match CalcEngines UI and display neatly on mobile.

1) Define Your Targets

  • VOUT and IOUT (load)
  • VIN_min / VIN_max (source range)
  • η (efficiency guess): 0.85–0.95 typical

2) Switching & Ripple

  • fSW (kHz): controller switching frequency
  • Inductor ripple % (ΔIL/IOUT): start at 30% (20–40% common)
  • VD (diode drop): used for stress approximations
Buck ripple is worst at VIN_max. The calculator sizes the inductor at high line accordingly.

3) Margins & Ripple Budget

  • MOSFET VDS margin: +20% to start
  • Diode VRRM margin: +40% (if asynchronous)
  • ΔVout (mVpp) for capacitive ripple and an ESR share (mVpp)
The tool separates capacitive and ESR ripple so you can pick Cout and its ESR independently.

4) Read the Results

  • Duty at VIN_max and VIN_min
  • L, ΔIL, IL,pk/val/rms
  • Mode check: CCM (OK) or May enter DCM
If it may enter DCM, increase L (reduce ripple %) or accept DCM and validate loop/EMI behavior on hardware.

5) Choose the Inductor

  • Pick a standard value ≥ L(calc)
  • Isat ≥ IL,pk with 20–30% margin
  • Irms rating ≥ IL,rms; low DCR reduces loss

6) Select MOSFET(s)

  • High‑side VDS rating ≥ VIN_max × margin
  • Current rating ≥ IL,pk; low RDS(on), reasonable Qg
  • If synchronous, match low‑side FET to diode currents (Irms, Ipk)

7) Choose Diode or Synchronous

  • Asynchronous: select a diode with VRRM ≥ VIN_max × margin, Iavg ≈ IOUT, Ipk ≈ IL,pk
  • Synchronous: low‑side MOSFET replaces diode for higher efficiency; ensure dead‑time and body‑diode/LS gate drive are correct

8) Output & Input Capacitors

  • Cout for capacitive ripple: ΔV ≈ ΔIL / (8 f C)
  • ESR ≤ ESRmax (from ESR ripple budget); check ripple current rating
  • Cin: place close to high‑side FET; ensure ripple current rating ≳ Iin,rms ≈ Iout·√(D·(1−D))

Quick Checklist

  • Duty at VIN_min/max reasonable
  • Inductor: L ≥ calc, Isat ≥ IL,pk, Irms ≥ spec
  • MOSFET: VDS & current margins OK
  • Diode or low‑side FET: VRRM/current margins OK
  • Cout & ESR meet ripple targets
  • Cin placed tightly; hot loop minimized
  • Bench: check VDS spikes, IL waveform, ΔVout
  • Thermal: inductor/FET/diode temps acceptable
FAQ & Tips

Mode shows “May enter DCM”. What now?
Increase the inductor (lower ripple %) or accept DCM and validate the control loop and EMI profile.

How much voltage headroom?
Start with about +20% on MOSFET VDS and +40% on diode VRRM (if used). Increase if ringing/surges are high.

Ripple too high even with big Cout?
Add polymers or MLCCs to lower ESR, add a small post‑LC, or raise fSW (if the controller allows).

When to go synchronous?
At higher currents or low VOUT, synchronous rectification usually gives meaningful efficiency gains and lower heating.

Copy‑Paste Mini Workflow

1) Fill VIN_min/max, VOUT, IOUT, η
2) Set fSW and ripple% = 30%
3) Margins: +20% MOSFET, +40% diode (if used); Ripple targets
4) Read Duty (min/max), L, IL_pk, stresses
5) Pick L ≥ calc; choose FET/diode (or sync FETs) with margins
6) Size Cout and Cin; verify ESR and ripple current ratings
7) Re‑iterate ripple%/fSW if stressed; build & validate