Boost Converter Design Calculator (CCM/DCM)

Boost Converter Design Calculator (CCM / DCM)

Topology: Non‑isolated Boost

Inputs

Worst case low line
0.8–0.95 typical
20–40% common
Capacitive portion

Key Results

Component Sizing

Notes: Uses worst‑case at VIN_min for duty and inductor sizing. Assumes CCM for core equations; calculator estimates DCM boundary and warns if your chosen ripple forces DCM. Thermal and loop design are out of scope here. Validate with hardware (ringing/snubber, layout, stability).

How to Use the Boost Converter Calculator

Follow these quick steps to size the inductor, switching device, diode, and output capacitor for a non‑isolated boost (with CCM/DCM awareness). Designed to match CalcEngines UI and work neatly on mobile.

1) Define Your Targets

  • VOUT & IOUT (load requirement)
  • VIN_min / VIN_max (source range)
  • η (efficiency guess): 0.85–0.95 typical

2) Switching & Ripple

  • fSW (kHz): controller switching frequency
  • Inductor ripple % (ΔIL/IL,avg): start at 30% (20–40% common)
  • VD (diode drop): 0.3–0.6 V Schottky, 0.7–1.2 V ultrafast

3) Margins & Ripple Budget

  • MOSFET VDS margin: +20% to start
  • Diode VRRM margin: +40%
  • ΔVout (mVpp) (capacitive portion) & ESR share (mVpp)
The calculator splits ripple into capacitive and ESR parts so you can size Cout and its ESR independently.

4) Read the Results

  • Duty @ VIN_min: worst case for boost
  • L, ΔIL, IL,pk/val/rms
  • Mode check: CCM (OK) or May enter DCM
If it may enter DCM, increase L (lower ripple %) or accept DCM and validate loop/EMI in hardware.

5) Choose the Inductor

  • Pick standard value ≥ L(calc)
  • Isat ≥ IL,pk (add 20–30% margin)
  • Irms rating ≥ IL,rms; low DCR preferred

6) Select the MOSFET

  • VDS rating ≥ (VOUT + Vd) × margin
  • I rating ≥ IL,pk; low RDS(on), reasonable Qg
  • Plan snubber/TVS if switch‑node ringing is observed

7) Select the Diode (or Synchronous)

  • VRRM ≥ (VOUT + Vd) × margin
  • Iavg ≈ IOUT, Ipk ≈ IL,pk
  • Schottky for low V, ultrafast for higher V/T; consider synchronous boost for top efficiency

8) Size the Output Capacitor

  • Cout from ΔV = IOUT·D / (f·C)
  • ESR ≤ ESRmax (from ESR ripple budget)
  • Check ripple current rating; polymer or MLCC banks help

Quick Checklist

  • Duty @ VIN_min reasonable (≲ 0.9)
  • Inductor: L ≥ calc, Isat ≥ IL,pk, Irms ≥ spec
  • MOSFET: VDS & I margins OK; snubber planned
  • Diode: VRRM & current OK (or sync rectifier)
  • Cout & ESR meet ripple targets
  • Board: tight hot loop, short switch node
  • Bench: check VDS spikes, IL waveform, ΔVout
  • Thermal: inductor/FET/diode temps acceptable
FAQ & Tips

It says “May enter DCM”. What now?
Increase L (reduce ripple %) to stay CCM at full load, or accept DCM and validate control/EMI—sometimes better light‑load efficiency.

How much voltage headroom?
Start with ~+20% on MOSFET VDS and ~+40% on diode VRRM. Raise if ringing/surges are high.

Ripple still high?
Increase Cout, reduce ESR, add post‑LC filter, or raise fSW (if controller allows).

Copy‑Paste Mini Workflow

1) Fill VIN_min/max, VOUT, IOUT, η
2) Set fSW and ripple% = 30%
3) Margins: +20% MOSFET, +40% diode; Ripple: 30 mV cap, 20 mV ESR
4) Read Duty, L, IL_pk, VDS/VRRM
5) Pick L ≥ calc; select MOSFET/diode with shown margins
6) Set Cout so ΔVcap ok and ESR ≤ ESRmax
7) Re-iterate ripple%/fSW if stressed; build & validate