Buck‑Boost Converter Design Calculator (Inverting & Non‑Inverting)

Buck‑Boost Converter Design Calculator (Inverting & Non‑Inverting)

Select Topology → Inverting (−Vout)

Inputs

Worst case low line
Negative for inverting; positive for non‑inverting
0.8–0.95 typical
Fraction of IL_avg (inv) or of mode‑specific avg (non‑inv)

Key Results

Component Sizing & Stresses

Notes:
  • Inverting mode: designs for −Vout. L sized against both VIN_min and VIN_max using your ripple %. Output ripple uses D at VIN_min. Switch/diode stresses use (VIN + |VOUT|) ideal sum plus margins.
  • Non‑inverting (4‑switch): chooses L large enough for both buck @ VIN_max and boost @ VIN_min. Device VDS stress ≈ max(VIN_max, VOUT). Capacitor ripple is max of buck and boost cases.
  • Thermal, switching losses, and loop design are outside scope—validate on hardware; add snubber/RC dampers as needed.

How to Use the Buck‑Boost Converter Design Calculator

A practical guide for both Inverting (−Vout) and Non‑inverting (+Vout, 4‑switch) buck‑boost modes. It matches your calculator UI and renders cleanly on mobile.

0) Pick the Topology

  • Inverting buck‑boost → set VOUT negative (e.g., −12 V). One main switch + diode (or sync FET).
  • Non‑inverting buck‑boost → set VOUT positive (e.g., +12 V). Four‑switch (two FET legs).
The calculator adapts equations per mode and shows the worst‑case results across VIN range.

1) Define Your Targets

  • VIN_min / VIN_max: true source range
  • VOUT: sign matters (negative for inverting, positive for non‑inverting)
  • IOUT and η (efficiency guess: 0.85–0.95 typical)

2) Switching & Ripple

  • fSW (kHz): controller switching frequency
  • Inductor ripple %: start at 30% (20–40% common)
  • VD (diode drop): used in stress/ripple estimates
Inverting: duty D ≈ |VOUT| / (VIN + |VOUT|) at each VIN.
Non‑inverting: use buck duty at VIN_max and boost duty at VIN_min; the tool picks worst‑case automatically.

3) Margins & Ripple Budget

  • Switch VDS margin: +20% to start
  • Diode VRRM margin: +40% (if asynchronous)
  • ΔVout (mVpp) for capacitive ripple and an ESR share (mVpp)
The tool separates capacitive and ESR ripple so you can pick Cout and its ESR independently.

4) Read the Results

  • Duty at VIN_min/VIN_max for the selected mode
  • L and ΔIL at both ends
  • IL,pk/val/rms and Mode check (CCM or may enter DCM)
If the tool warns about DCM, increase L (reduce ripple %) or accept DCM and validate loop/EMI on hardware.

5) Choose the Inductor

  • Pick a standard value ≥ L(calc) that meets both ends (and both modes for non‑inverting)
  • Isat ≥ IL,pk with 20–30% margin
  • Irms rating ≥ shown worst‑case; low DCR reduces loss

6) Switches & Diode

  • Inverting: switch/diode VDS/VRRM ≈ VIN_max + |VOUT| + Vd (then apply your margin)
  • Non‑inverting: each FET VDS ≈ max(VIN_max, VOUT) (then apply margin)
  • Match current ratings: Ipk, Irms; prefer low RDS(on) and reasonable Qg

7) Output & Input Capacitors

  • Cout for capacitive ripple:
    Inverting/Boost case: ΔV ≈ IOUT · D / (f · C) (worst at VIN_min)
    Buck case: ΔV ≈ ΔIL / (8 f C) (worst at VIN_max)
  • ESR ≤ ESRmax (from ESR ripple budget); check ripple current rating
  • Cin: place close to switches; ensure ripple current rating ≳ Iin,rms

Quick Checklist

  • Topology matches sign of VOUT
  • Duty at VIN_min/max reasonable
  • Inductor: L ≥ calc, Isat ≥ IL,pk, Irms ≥ spec
  • Switch/Diode (or FETs): VDS/VRRM and current margins OK
  • Cout & ESR meet ripple targets (worst of modes)
  • Cin tight to switches; hot loop minimized
  • Bench: check VDS spikes, IL waveform, ΔVout
  • Thermal: inductor/FET/diode temps acceptable
FAQ & Tips

Why does the tool show two duties/ripples?
Because worst‑case differs across VIN and between buck vs. boost behavior. The calculator picks the governing case for sizing.

Mode shows “May enter DCM”. What now?
Increase L (lower ripple %) to stay CCM at full load, or accept DCM and validate the control loop and EMI profile.

How much voltage headroom?
Start with about +20% on switch VDS and +40% on diode VRRM (if used). Increase if ringing/surges are high.

Ripple still high?
Add polymers/MLCCs to lower ESR, add a small post‑LC, or raise fSW (if the controller allows).

Copy‑Paste Mini Workflow

1) Pick topology; set VIN_min/max, VOUT (sign), IOUT, η
2) Set fSW and ripple% = 30%; enter diode drop, rectification type
3) Margins: +20% switch VDS, +40% diode VRRM; set ripple targets
4) Read duties, L, IL_pk/val/rms; check CCM/DCM note
5) Choose inductor ≥ calc; select switch/diode (or FETs) with margins
6) Size Cout (worst of modes) and Cin; verify ESR and ripple ratings
7) Re‑iterate ripple%/fSW if stressed; build & validate