BJT Biasing Calculator (Voltage-Divider Bias)

The four-resistor bias that every small-signal transistor stage is built on: divider, emitter and collector resistors to an operating point, the voltage gain and impedances that follow from it, and the number that justifies the whole topology — how far the collector current moves when β doubles. Design mode goes the other way, from a target IC and VCE to four E24 resistors.

Voltage-divider bias, and the small-signal stage on top of it

The same nominal operating point, two ways of getting there

Biasing a transistor for linear operation

A bipolar transistor amplifies because its collector current follows its base–emitter voltage, and the job of a bias network is to hold that current steady at a chosen value so the signal has somewhere to swing. Four resistors do it: R1 and R2 make a divider that sets the base voltage, R_E turns that voltage into a current, and R_C turns the current back into a voltage at the output. This is the linear case. It is a different problem from the one on the BJT as a switch calculator, which deliberately drives the transistor hard into saturation so that V_CE collapses to a couple of tenths of a volt: there the base current is made several times larger than β alone requires, and β’s variability is handled by brute force. Here the transistor must sit in the middle of the active region, and brute force is not available — so the circuit is arranged so that β hardly matters.

Why this topology at all. Bias a transistor with a single resistor from the supply to the base and the base current is fixed, so the collector current is β times a constant — and β is a datasheet minimum that varies three to one between samples of the same part number, rises with temperature and falls with current. The stage would work on one transistor and saturate on the next. The divider fixes the base voltage instead, and R_E converts it to a current: I_E ≈ (V_B − V_BE)/R_E, with no β in it. The exact expression, I_B = (V_th − V_BE) ÷ (R_th + (β+1)R_E), shows the condition: the term (β+1)R_E must dominate R_th. That is the real content of the rule of thumb that the divider current should be at least ten times the base current. At the defaults here, doubling β from 200 to 400 moves the collector current by 4.43%; with fixed base current it would move by 100%.

Choosing the operating point. Put the emitter at about a tenth of the supply — enough that V_BE‘s −2 mV/°C drift is a small fraction of it, little enough that you have not thrown away headroom. Pick the collector current from the gain and noise you want and from what the next stage needs. Then R_C takes whatever is left of the supply after V_CE and V_E, and V_CE should leave room for the output to swing both ways. Design mode above does exactly that and then rounds all four resistors to standard values, because what you can buy is what you will build with — and it re-solves the circuit with the rounded values, so the operating point shown is the one you get, not the one you asked for.

Gain, and the price of it. The small-signal transconductance is g_m = I_C/V_T, where V_T = kT/q is 25.69 mV at 25 °C and rises with temperature. With R_E bypassed by a capacitor the voltage gain is −g_m(R_C∥R_L) — 234.3 at the defaults — but it is proportional to I_C and inversely proportional to temperature, so it is not a number you can rely on to better than tens of per cent. Leave R_E unbypassed and the gain becomes roughly −R_C/R_E, a ratio of two resistors, which is stable and predictable and far smaller: −4.57 here. That trade — gain for predictability — is the reason op-amp gain stages exist, and it is worth seeing it once in a single transistor before taking feedback for granted. The input impedance is R1 ∥ R2 ∥ (the impedance looking into the base), so a stiff divider costs input impedance: 1.53 kΩ here, most of it r_π.

What this model leaves out. A constant V_BE rather than an exponential one (worth about 2% in the collector current at these levels — checked here against a Newton solve of the exponential model), the Early effect, so the output impedance is shown as R_C alone rather than R_C∥r_o; the base-spreading resistance; and every frequency effect, so there is no bandwidth here at all — the bypass and coupling capacitors set the low-frequency corner and the RC filter calculator will size them. Every DC and small-signal formula above was checked against a nodal solve of the actual network — a conductance matrix for the small-signal case and a direct three-equation solve for the bias — rather than against a rearrangement of itself.

Frequently asked questions

Related calculators

References

1. Sedra AS, Smith KC, Carusone TC, Gaudet V. Microelectronic Circuits, 8th ed. Oxford University Press, 2020. Chapter 6: biasing a BJT amplifier — the classical four-resistor arrangement, the condition R_th ≪ (β+1)R_E for β-independent bias, the rule of thumb of setting V_E to about V_CC/3 or V_CC/10, and the hybrid-π small-signal model.
2. Horowitz P, Hill W. The Art of Electronics, 3rd ed. Cambridge University Press, 2015. Chapter 2: the common-emitter amplifier, emitter degeneration, g_m = I_C/V_T and the intrinsic emitter resistance r_e = V_T/I_C.
3. onsemi. 2N3903, 2N3904 general purpose transistors, publication order number 2N3904/D. h_FE 100 minimum and 300 maximum at 10 mA — the three-to-one spread within a single part number that this bias arrangement exists to absorb.
4. IEC 60063:2015. Preferred number series for resistors and capacitors (E24 and E96), used for the standard values in design mode.