Crystal Load Capacitor Calculator

The two capacitors a Pierce oscillator needs, from the crystal’s specified load capacitance and the stray capacitance of your board and the chip’s own pins — plus the part nobody prints: how far off frequency the nearest standard value puts you, and whether the oscillator has enough gain to start at all.

Load capacitors, frequency pulling and gain margin

What the nearest standard capacitor costs you

Loading a crystal correctly

A quartz crystal is not a frequency. It is a very high-Q resonator whose exact frequency depends on what it is connected to, and the manufacturer calibrates it against a specified load capacitance — 12 pF, 18 pF, 20 pF are common. Present a different load and it runs at a different frequency. In a Pierce oscillator, the commonest arrangement by far, the load is the two capacitors from the oscillator pins to ground, in series as far as the crystal is concerned, plus whatever stray capacitance the pins and the tracks add: C_L = C1·C2/(C1+C2) + C_stray. Two equal capacitors in series make half of one, so each has to be twice the remainder.

The stray is not a rounding error. A microcontroller’s OSC_IN and OSC_OUT pins carry a few picofarads each, and a centimetre of track over a ground plane adds roughly half a picofarad more. On a 12 pF crystal, 5 pF of stray takes the external capacitors from 24 pF down to 14 pF — nearly half. Leaving it out is the commonest reason a board runs fast: the real load is higher than intended, and — this is the direction that catches people — a crystal with too much load capacitance runs slow, not fast. Leaving the stray out of the calculation makes the fitted capacitors too big, which makes the total load too big, which makes the clock slow. The arithmetic is worth doing twice.

Why too much load means slow. Between its series and parallel resonances a crystal looks inductive, and the load capacitance resonates against it. The Butterworth–Van Dyke model — a motional branch L_m, C_1m, R_m in series with the static capacitance C₀ across it — gives the load resonance exactly as f_L = f_s·√(1 + C_1m/(C₀+C_L)), which to well under a part per million is f_s(1 + C_1m/(2(C₀+C_L))). Increase C_L and that correction shrinks, so the frequency falls back towards the series resonance. The whole range available is C_1m/(2(C₀+C_L)) — only 441.2 ppm on this crystal — which is why a crystal is stable and also why it cannot be pulled far. Differentiating gives the trim sensitivity, C_1m/(2(C₀+C_L)²): 25.95 ppm per picofarad here, falling as the square of the load. Every one of those relations was checked on this page by root-finding the actual reactance of the equivalent circuit rather than by trusting the series expansion.

Will it start? Getting the frequency right is no use if the oscillator never runs. The amplifier presents a negative resistance to the crystal — a nodal solve of the inverter with C1 and C2 gives |R_neg| = g_m/(ω²·C1·C2), which is derived and checked here — and oscillation starts only while that exceeds the crystal’s losses. Because C₀ shunts the motional branch, the loss the amplifier actually has to overcome is ESR × (1 + C₀/C_L)², and putting the two together gives ST’s criterion g_m,crit = 4·ESR·(2πF)²·(C₀+C_L)², with a gain margin of at least 5 asked for on a high-speed oscillator and 3 on a 32.768 kHz one. That margin is where low-power designs fail: a tuning-fork crystal has an ESR of 50–90 kΩ against 80 Ω here, and a watch oscillator has microamps per volt of transconductance rather than milliamps. Bigger load capacitors always make starting harder, because gm,crit goes as the square of the load.

Drive level, and the rest of the layout. Too much current through a crystal ages the quartz, shifts the frequency and eventually cracks the blank; the datasheet gives a maximum drive level in microwatts and DL = ESR × I², so the RMS current limit is √(DL/ESR) — 1.118 mA here. A series resistor at OSC_OUT is the usual way to reduce it, at the cost of gain margin. Keep the whole loop short, put a ground pour under it and nothing else near it, and bring the crystal’s ground and both capacitors’ grounds to one point. For the digital side of the clock see the PWM duty cycle calculator; for an RC-timed oscillator instead of a crystal, the 555 astable calculator; and for the LC resonance this is the quartz analogue of, the LC resonant frequency calculator. Use the figures from your part’s datasheet; typical values vary widely between manufacturers.

Frequently asked questions

Related calculators

References

1. STMicroelectronics. AN2867: Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs, Rev. 24, February 2026. C_L = (C_L1·C_L2)/(C_L1+C_L2) + C_s; g_m,crit = 4 · ESR · (2πF)² · (C₀+C_L)² with a gain margin above 5 for HSE and above 3 for LSE; drive level DL = ESR · I_Q² and I_Qmax,pp = 2√(2·DL_max/ESR).
2. Renesas. AN-831: Crystal Load Curve, Rev. B. The load resonance F_L² = F_R²·(1 + C1/(C0+C_L)), and the trim sensitivity dF/dC_L = −C1/(2(C0+C_Ln)²) in parts per million per picofarad.
3. Vittoz EA, Degrauwe MGR, Bitz S. High-performance crystal oscillator circuits: theory and application. IEEE Journal of Solid-State Circuits, vol. 23 no. 3, June 1988, pp. 774–783. doi:10.1109/4.318. The negative resistance of the three-point oscillator and the critical transconductance for start-up.
4. IEC 60063:2015. Preferred number series for resistors and capacitors (E12 and E24), used for the standard capacitor values suggested here.