Control Loop Stability Calculator

Enter a loop gain — a DC or integrator term, a resonant pole pair, zeros and poles — or let the page build the plant from a buck output stage, and get the crossover frequency, the phase margin, the gain margin and the step-response overshoot that phase margin implies, with the Bode plot that shows where they are read.

Last updated 24 Sep 2026

Crossover, phase margin and gain margin from a loop gain

Poles and zeros → margins

Where does the plant come from?Option 2 computes the double pole, its Q, the output capacitor’s ESR zero and the modulator-plus-power-stage gain from the components below, and writes them into the four fields under it. Option 1 leaves those four as your own inputs — which is what you want for a current-mode loop, a boost, an LDO, a motor drive or any loop whose plant you already have from a measurement or a simulation.

Output inductor (µH)Only used when the plant is built from components.

Output capacitance (µF)The total effective capacitance at the output. For ceramics this is the capacitance that survives the DC bias, not the marked value.

Output capacitor ESR (mΩ)This sets the zero at 1 ÷ (2π·ESR·C). With a ceramic output capacitor that zero is far above the switching frequency and does nothing useful, which is exactly why an all-ceramic output is harder to compensate than an electrolytic one.

Inductor DCR (mΩ)Damps the output resonance a little and drops the DC gain a little.

Load resistance at the operating point (Ω)Output voltage divided by output current. The Q of the output resonance rises as the load gets lighter, so check the loop at light load as well as at full load — that is usually where the margin is worst.

Input voltage (V)For a voltage-mode buck the modulator gain is V_in ÷ V_ramp, so the loop gain moves with the input voltage unless the controller feeds it forward.

PWM ramp amplitude (V)The peak-to-peak ramp the error voltage is compared against. Typically 1 V to 2 V. Use the figures from your part’s datasheet; typical values vary widely between manufacturers.

Plant double-pole frequency f₀ (Hz)The resonance of the output filter, or whatever pole pair your plant has. Enter 0 if the plant has no resonant pair. With the second option selected this field is locked and shows what the components give.

Q of that pole pairHow sharp the resonance is. A lightly loaded LC output with a low-ESR ceramic capacitor can easily reach Q = 10; the same stage at full load with an electrolytic sits near 1.

Plant zero (Hz), 0 for noneThe output capacitor’s ESR zero in a converter.

Flat gain ahead of the loop (dB)Everything that is frequency-independent: the modulator gain, the power-stage DC gain, the feedback divider. Negative is allowed.

Is there an integrator in the loop?Almost every regulator has one, because it is what makes the output voltage independent of load at DC. It costs a fixed 90° of phase at every frequency.

Integrator unity-gain frequency (Hz)The frequency at which the compensator’s integrator ALONE would have a gain of one. Raising it raises the whole loop gain and moves the crossover up. Ignored when there is no integrator.

Compensator zero 1 (Hz), 0 for noneA zero adds up to 90° of phase and +20 dB/decade of gain. Put it at or just below the plant’s resonance to cancel the phase the resonance takes away.

Compensator zero 2 (Hz), 0 for noneA type III compensator has two. Two zeros near the resonance are what make a voltage-mode LC loop crossable well above f₀.

Compensator pole 1 (Hz), 0 for nonePut it at the ESR zero to cancel it, or above crossover to roll the loop off before the switching frequency.

Compensator pole 2 (Hz), 0 for noneUsually placed at half the switching frequency, to keep switching ripple out of the error amplifier.

Right-half-plane zero (Hz), 0 for noneA boost, buck-boost, flyback or SEPIC in continuous conduction has one. It raises the gain like a zero and drops the phase like a pole — the worst of both — and there is no compensator that cancels it. Crossing below about a fifth of it is the usual rule.

Extra delay (µs), 0 for noneThe modulator’s sampling behaviour, a digital controller’s computation and PWM update, an isolator, a communication link. A pure delay costs phase in proportion to frequency and nothing in gain, so it never shows up in a gain plot and is the commonest reason a loop that looked fine on paper rings. Half a switching period is a reasonable first estimate for the modulator alone: 1 µs at 500 kHz.

The loop drawn as a block diagram rather than as a full schematic, because the subject is the loop and not any one converter. The error amplifier and its compensator network are real components — the compensator's zeros and poles are the frequencies you enter — while the modulator and the power stage are one block, since the page takes their combined flat gain as a single number and their dynamics as the pole pair and the zero beside it. The three figures underneath are where the loop crosses 0 dB, how much phase is left there, and how much the gain could rise at the frequency where the phase reaches −180°.

56.8°Example

a 12 V voltage-mode buck with a 22 µH inductor, 100 µF of output capacitance at 20 mΩ ESR, 3.3 Ω of load, a 1 V PWM ramp, a type III compensator whose integrator alone reaches unity at 1.2 kHz with zeros at 2 kHz and 3.2 kHz and poles at 60 kHz and 160 kHz, and 1.0 µs of modulator delay

Everything adds, because the axes are logarithmic

|L(jf)|_dB = G_flat + 20·log₁₀(f_i/f) − 10·log₁₀[(1 − (f/f₀)²)² + (f/(Q·f₀))²] + Σ 10·log₁₀(1 + (f/f_z)²) − Σ 10·log₁₀(1 + (f/f_p)²)
∠L(jf) = −90° − atan2(f/(Q·f₀), 1 − (f/f₀)²) + Σ atan(f/f_z) − Σ atan(f/f_p) − 2π·f·T_d
φ_m = 180° + ∠L(jf_c) where |L(jf_c)| = 1
Q_closed = √(cos φ_m) ÷ sin φ_m, ζ = sin φ_m ÷ (2√(cos φ_m)), overshoot = exp(−πζ/√(1−ζ²))

f_c: the crossover frequency: where the loop gain’s magnitude is exactly one. Found here by bracketing on a 19-point logarithmic grid and bisecting inside the bracket, because a loop can cross 0 dB more than once
φ_m: phase margin: how much further the phase could fall at f_c before the feedback becomes positive there
gain margin: how much further the gain could rise, in decibels, at the frequency where the phase reaches −180°
T_d: pure delay. Costs phase in proportion to frequency and nothing in gain, so it is invisible in a gain plot
ζ, Q: the damping of the second-order closed loop that has this phase margin. Exact for L(s) = ωₙ²/(s(s+2ζωₙ)) and a good guide for anything that crosses at −20 dB/decade

Worked example

a 12 V voltage-mode buck with a 22 µH inductor, 100 µF of output capacitance at 20 mΩ ESR, 3.3 Ω of load, a 1 V PWM ramp, a type III compensator whose integrator alone reaches unity at 1.2 kHz with zeros at 2 kHz and 3.2 kHz and poles at 60 kHz and 160 kHz, and 1.0 µs of modulator delay
The output stage resonates at 3.396 kHz with Q = 4.223, and the capacitor's ESR puts a zero at 79.58 kHz. The modulator and power stage together contribute a flat 21.52 dB — that is 12 ÷ 1 reduced slightly by the inductor's DCR
The loop gain passes 0 dB at 25.31 kHz. That is found by evaluating the gain at 19 logarithmically spaced frequencies, taking the highest grid cell in which it changes sign, and bisecting 18 times inside that one cell
At that frequency the phase has fallen to -123.2°, so the phase margin is 56.8°. The 1.0 µs of delay accounts for 9.1° of that fall on its own
The phase reaches −180° at 121.6 kHz, where the gain has fallen to −17.30 dB — a gain margin of 17.30 dB
A phase margin of 56.8° corresponds to ζ = 0.565 and a closed-loop Q of 0.884, so a load step should overshoot about 11.6%, ring at 28.21 kHz and settle to within 2% in about 32.9 µs

What a phase margin means, in numbers rather than adjectives

Computed from Q = √(cos φ) ÷ sin φ and overshoot = exp(−πζ/√(1−ζ²)), the exact relations for a loop that crosses at −20 dB/decade with a single pole above it. Erickson and Maksimović give the same relation and the same two landmarks — φ = 52° for Q = 1 and φ = 76° for Q = 0.5 — in §9.4.2. Note where critical damping actually is: 76°, not 60°.
Phase margin	Closed-loop Q	Damping ratio ζ	Step overshoot	In practice
20.0°	2.834	0.176	56.9%	rings for many cycles; almost no margin for the plant to move
30.0°	1.861	0.269	41.6%	visibly underdamped; the usual absolute floor
45.0°	1.189	0.420	23.3%	a common minimum design target
52.0°	0.996	0.502	16.1%	the classic Q = 1 point
60.0°	0.816	0.612	8.8%	the usual aim: fast, with modest overshoot
70.0°	0.622	0.803	1.4%	well damped, noticeably slower
76.3°	0.501	0.998	0.0%	critically damped — the fastest response with no overshoot
85.0°	0.296	1.687	none	overdamped; bandwidth is being given away

Reading a Bode plot, and the four things this model leaves out

A feedback loop is stable when, at the frequency where its own gain is exactly one, the signal coming back is not yet in phase with the signal going out. That is the whole idea. Crossover is the frequency where the loop gain passes through 0 dB; phase margin is how far the phase still is from −180° there; gain margin is the mirror image — how much the gain could rise at the frequency where the phase does reach −180°. A design with 45° to 60° of phase margin and 10 dB or more of gain margin is what most people mean by a well-compensated loop.

Why the chart plots 180° + ∠L rather than ∠L. The two things you read off a Bode plot are a gain crossing zero decibels and a phase crossing −180°. Plotting the phase as the margin that remains puts both readings on the same line: where the blue gain curve meets the zero line is the crossover, the amber curve’s height there is the phase margin, and where the amber curve meets the zero line is the frequency the gain margin is measured at. One reference line, two readings, and no second axis to get confused about.

What the phase margin tells you about the step response. For a loop that crosses at −20 dB/decade, the closed-loop pole pair has Q = √(cos φ) ÷ sin φ, so the phase margin converts directly into a damping ratio and an overshoot. 45° is Q = 1.19 and about 23% overshoot; 52° is Q = 1 exactly; 60° is Q = 0.82 and about 9%; critical damping — no overshoot at all — arrives at 76.3°, not at 60° as it is often loosely said. Above that the loop is overdamped and you are paying bandwidth for a response that was already monotonic.

What this page is not about. A converter also has an input filter, and an input filter interacts with the converter through the NEGATIVE incremental input impedance a regulated converter presents — Middlebrook’s criterion. That is a different loop, with a different failure mode: a working converter that oscillates when a filter is put in front of it, with the control loop untouched and perfectly healthy. The input filter calculator owns that question and this page does not touch it. Conversely that page says nothing about the control loop. A converter can fail either test independently, and needs both.

Four things this linear model leaves out, all of which eat margin. First, large-signal behaviour: duty-cycle saturation, current limit and the error amplifier’s own slew rate are nonlinearities that a small-signal model cannot see, and a loop with 60° of margin can still recover badly from a big step. Second, sampling: a PWM modulator samples once a cycle and a digital controller adds a computation delay on top, and both appear as pure delay — put an estimate into the delay field and watch the margin fall. Third, the plant moving: the output resonance’s Q rises as the load gets lighter and ceramic capacitance falls with DC bias, so the loop you compensated at full load is not the loop you ship. Fourth, everything above the switching frequency, where a small-signal averaged model stops being valid at all.

For the power stage itself, the buck designer and the boost designer size the inductor and capacitors and give the boost’s right-half-plane zero, which is the number to put in the RHP field here. For the amplifier that implements the compensator, the non-inverting amplifier page gives the gain-bandwidth and slew limits it has to meet.

Frequently asked questions

How much phase margin do I actually need?

45° to 60° is the usual target and the reason is not aesthetic: it is the range in which the step response settles quickly without overshooting much, and there is enough margin left for the plant to move with load, temperature and component tolerance. Below 30° a loop rings badly and has almost nothing in reserve; above 80° it is overdamped and you are giving away bandwidth. Gain margin is usually asked to be at least 10 dB alongside it.

The page says the gain margin is unbounded. Is that real?

No — it is a property of the model. If you enter an integrator, a resonant pair, a few zeros and the same number of poles, the phase can asymptote to −180° without ever crossing it, and the model then has no phase crossover frequency. Real hardware always has more poles and always has delay. Put a realistic delay in — half a switching period is a reasonable first estimate for a PWM modulator — and a finite gain margin appears.

Why does the crossover move when I change the load?

Two reasons. The Q of the output resonance rises as the load gets lighter, which lifts the gain near f₀; and in a voltage-mode converter the modulator gain is V_in ÷ V_ramp, so the loop gain moves with the input voltage too unless the controller feeds it forward. Check the loop at the corners — light load and high input — not just at the nominal operating point.

What is the difference between this and the input filter page?

They are different loops. This page is about the CONTROL loop: the error amplifier, the modulator, the power stage and the feedback divider. The input filter page is about the interaction between an LC filter and the negative incremental input impedance a regulated converter presents at its input terminals, which can make a converter oscillate with its control loop completely untouched. A design has to pass both, and passing one says nothing about the other.

My loop crosses 0 dB three times. Which margin does the page report?

The one at the highest crossing, which is the conventional choice, and the page says so in the note when it happens. But a loop with several crossings is genuinely not described by one number: the honest test is the Nyquist criterion, which counts encirclements of −1 rather than reading a margin at one frequency. Read the plot, and if the answer matters, do the Nyquist plot properly.

Can I use this for a current-mode converter?

Yes, but do not use the buck-output-stage option: in current mode the inductor is inside an inner loop and the outer plant is closer to a single pole formed by the output capacitor and the load, plus the sampling-and-hold effect near half the switching frequency. Enter that plant yourself with the first option — a single pole, no resonant pair (set f₀ to 0), the ESR zero, and a delay to represent the sampling.

Related calculators

References

R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 3rd edition, Springer 2020. Chapter 9 is the reference for this page: §9.4.1 defines the crossover frequency as the frequency where |T(j2πf_c)| = 1 and the phase margin as φ_m = 180° + ∠T(j2πf_c); §9.4.2 gives the closed-loop Q as a function of phase margin, with φ_m = 52° for Q = 1 and φ_m = 76° for Q = 0.5; §9.5 covers lead (PD), lag (PI) and combined PID compensators and §9.5.4 works a complete design. Verified against the publicly posted chapter 9 slide set, whose section numbering and the two Q landmarks are reproduced above; this page’s damping relation, derived independently and checked against a numerical crossover solve, gives Q = 1.000 at 52° and Q = 0.507 at 76°.
H. W. Bode, Network Analysis and Feedback Amplifier Design, Van Nostrand, 1945. The origin of the gain and phase plots this page draws and of the gain- and phase-margin definitions used on it.
R. D. Middlebrook, “Input filter considerations in design and application of switching regulators”, IEEE Industry Applications Society annual meeting, 1976. Cited here only to mark the boundary: the interaction it describes is between an input filter and a converter’s negative input impedance, and is a different stability question from the one this page answers.
Texas Instruments, Basic Calculation of a Buck Converter’s Power Stage, application report SLVA477B. The power-stage relations the buck option here assumes — duty cycle, inductor ripple, output capacitor — in their standard form. Document number and title verified against Texas Instruments’ own listing.