Flyback Converter Calculator

Flyback Converter Calculator

First-pass flyback design from the input range, output and switching frequency: turns ratio, reflected voltage, primary (magnetising) inductance, peak and RMS primary current, MOSFET drain voltage stress and output diode reverse voltage.

Flyback power stage

Vin range, Vout, Pout → n, Lp, stresses
For mains input, the lowest bulk-capacitor voltage (the valley) at the lowest line voltage — about 100 V for 85 V AC with a typical bulk capacitor.
For mains, the peak of the highest line voltage: 265 V AC × √2 ≈ 375 V.
An estimate: 80–90% is typical for a small offline flyback.
Used when the turns ratio is set by duty. Controllers often limit it; check yours.
Used when the turns ratio is set by reflected voltage.
ΔI ÷ (2 × average on-time current), AN4137’s definition. Below 1 is CCM at minimum input and full load; 1 is the CCM/DCM boundary.
Use the figures from your part’s datasheet; typical values vary widely between manufacturers.
The overshoot the clamp or snubber allows above Vin + reflected voltage. Set it from your clamp design.
Flyback: while the MOSFET is on, the primary stores energy in the magnetising inductance Lm; when it turns off, the windings' opposite dots let that energy flow out through the diode. The dots show average currents at minimum input; the real currents are pulses at the switching frequency. Safety: from the mains, the DC bus is rectified line voltage, lethal and not isolated, and it stays charged after unplugging.
1.103mHExample

Universal mains: 100–375 V DC bus, 12 V at 24 W, 65 kHz, 85% efficient, 45% maximum duty, KRF 0.5, 0.5 V diode, 100 V spike allowance

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Flyback design equations (AN4137)

VR = Vin,min·Dmax ÷ (1 − Dmax); n = Np/Ns = VR ÷ (Vo + VF); Lm = (Vin,min·Dmax)² ÷ (2·Pin·f·KRF); Ipk = IEDC + ΔI/2, IEDC = Pin ÷ (Vin,min·Dmax); VDS = Vin,max + VR + Vspike; VD = Vo + Vin,max/n
Pin
Pout ÷ efficiency
KRF
ripple factor ΔI ÷ (2·IEDC); 1 = boundary between CCM and DCM
VR
output voltage reflected to the primary while the diode conducts
Vspike
leakage-inductance overshoot allowed by the clamp

Worked example

Universal mains: 100–375 V DC bus, 12 V at 24 W, 65 kHz, 85% efficient, 45% maximum duty, KRF 0.5, 0.5 V diode, 100 V spike allowance
Pin = 24 ÷ 0.85 = 28.24 W
VR = 100 × 0.45 ÷ 0.55 = 81.8 V; n = 81.82 ÷ 12.5 = 6.545
Lm = (100 × 0.45)² ÷ (2 × 28.24 × 65,000 × 0.5) = 1.103 mH
IEDC = 28.24 ÷ 45 = 627.5 mA; ΔI = 627.5 mA; peak 941.2 mA, RMS 438.1 mA
VDS = 375 + 81.8 + 100 = 557 V; diode VR = 12 + 375 ÷ 6.545 = 69.3 V

How the flyback numbers fit together

A flyback converter is a buck-boost whose inductor has two windings. While the MOSFET is on, the primary stores energy in the transformer’s magnetising inductance; when it turns off, the energy flows out of the secondary through the diode. Two choices set most of the design: the turns ratio, and how deep into continuous conduction the converter runs at low line.

Turns ratio. While the diode conducts, the output voltage (plus the diode drop) is reflected back to the primary multiplied by the turns ratio. Volt-second balance at minimum input and full load ties that reflected voltage to the maximum duty cycle: VR = Vin,min·D/(1 − D). A higher VR lowers the primary current but adds directly to the MOSFET’s drain voltage. In the example, 45% duty gives 81.8 V and a turns ratio of 6.545, and the drain sees about 557 V at high line with a 100 V spike allowance, so a 650 V MOSFET would be a usual choice; the diode must block about 69.3 V.

Inductance and the ripple factor. AN4137’s ripple factor KRF compares the peak-to-peak primary current ripple with twice the average current during the on-time. At KRF = 1 the current just reaches zero each cycle (the CCM/DCM boundary); smaller values run deeper into CCM with a larger inductance and a lower peak and RMS current. The note suggests lower values for universal input than for 230 V-only designs. Because the inductance is chosen at minimum input, the converter usually moves into DCM at high line; the page tells you which mode it is in at maximum input and gives the duty and peak current there.

What this page does not do. It does not choose a core, wind the transformer, size the clamp or snubber, or check the loop. Leakage inductance, which makes the drain spike, depends on the winding. The SMPS transformer calculator planned for this section will take the turns ratio and inductance on to the core and windings. For the MOSFET’s losses use the MOSFET loss calculator.

Safety. An offline flyback has a rectified mains bus of several hundred volts on the primary, and the bulk capacitor stays charged after the plug is pulled. The transformer’s insulation and creepage distances carry the safety isolation and are set by product safety standards, not by this arithmetic. Mains voltage can kill. This page does the arithmetic only; for anything connected to the supply, follow your local electrical code and have the work done or checked by a licensed electrician.

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Frequently asked questions

How do you calculate the turns ratio of a flyback transformer?

Choose the maximum duty at minimum input, work out the reflected voltage VR = Vin,min × D ÷ (1 − D), then n = Np/Ns = VR ÷ (Vout + Vdiode). For 100 V, 45% and 12 V out with a 0.5 V diode: 81.8 ÷ 12.5 = 6.545.

How do you calculate the primary inductance of a flyback?

Lm = (Vin,min × Dmax)² ÷ (2 × Pin × f × KRF). With KRF = 1 it sits at the CCM/DCM boundary; below 1 it runs in CCM. The example gives 1.103 mH; at KRF = 1 it would be 551.7 µH.

What voltage does the flyback MOSFET see?

The maximum DC input plus the reflected voltage plus the leakage spike the clamp allows: 375 + 81.8 + 100 ≈ 557 V in the example.

What reverse voltage does the output diode see?

The output voltage plus the maximum input divided by the turns ratio: 12 + 375 ÷ 6.545 = 69.3 V, before any ringing.

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References

  1. Fairchild Semiconductor (now onsemi). Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS). Application note AN-4137, 2003. Ripple factor KRF, Lm = (VDC,min·Dmax)² ÷ (2·Pin·fs·KRF), VRO, turns ratio, drain and diode voltage stress.
  2. Erickson RW, Maksimović D. Fundamentals of Power Electronics, 3rd ed. Springer, 2020. Ch. 2 (inductor volt-second and capacitor charge balance, ripple), Ch. 5 (the CCM–DCM boundary), Ch. 8, Table 8.2 (right-half-plane zero: D′²R/L for the boost, D′²R/(DL) for the buck-boost).
  3. Mohan N, Undeland TM, Robbins WP. Power Electronics: Converters, Applications, and Design, 3rd ed. Wiley, 2003. Ch. 10, flyback converter.