Push-Pull Converter Calculator

Centre-tapped push-pull power stage: turns ratio, the duty cycle per switch and the dead time between them, the output inductor and capacitor, the 2 × Vin the off switch stands at, the peak flux in the core — and how fast a volt-second mismatch walks that flux into saturation, which is the reason this topology is normally run under current-mode control.

Reviewed by Jithin K Sajeev, Power Electronics Specialist & Embedded Systems Engineer Holds a Master of Technology (M.Tech) in Power Electronics & Drives and a B.Tech in Electrical & Electronics Engineering. With over 11 years of hands-on industry experience designing high-reliability power conversion and electronic systems, he reviews CalcEngines tools for mathematical rigor, real-world engineering constraints, and standard compliance.Last reviewed 24 Sep 2026

Push-pull power stage

Vin range, Vout, Iout → turns, Lo, stresses

Minimum DC input (V)The turns ratio is set here, at the maximum duty cycle.

Maximum DC input (V)Sets the output-inductor ripple and every voltage stress. The switches see twice this figure.

Output voltage (V)

Output current (A)

Switching frequency per switch (kHz)Each switch runs at this rate; the output inductor and capacitor see twice it, because both halves of the transformer feed the same rectifier.

Maximum duty cycle per switch at minimum input (%)Each switch, on its own, must stay below 50%. What is left over, 1 − 2·D, is the dead time in which neither switch conducts — and it has to be real, or both halves of the primary conduct at once and short the transformer.

Output diode forward drop (V)One diode is always in the output path, in both the conducting and the freewheel intervals. Enter 0 for synchronous rectifiers. Use the figures from your part’s datasheet; typical values vary widely between manufacturers.

Output inductor ripple (% of output current)Peak to peak, at maximum input. 20–40% is usual.

Output ripple target (mV peak to peak)

Primary turns per halfOne half of the centre-tapped primary. The two halves must be wound identically — interleaved or bifilar — or their leakage inductances differ and the flux imbalance below gets worse.

Core effective area A_e (mm²)From the core’s data sheet. 97.1 mm² is an ETD34, 125 mm² an ETD39, 76 mm² an ETD29. Use the figures from your part’s datasheet; typical values vary widely between manufacturers.

Usable peak flux density (mT)Saturation at the hottest the core will run, not at 25 °C: about 390 mT for a power ferrite such as 3C90/N87 at 100 °C, against 490 mT cold. Use the hot figure. Use the figures from your part’s datasheet; typical values vary widely between manufacturers.

Volt-second mismatch between the two halves (%)How unequal the two on-times or the two switch drops are. 1% is a realistic figure for matched parts and a symmetrical layout. This is what walks the flux into saturation.

Centre-tapped push-pull. Q1 and Q2 conduct alternately, each for less than half the period, so each half of the primary sees the input in turn and the off switch stands at twice it. The centre-tapped secondary rectifies both halves into the same output inductor, which therefore ripples at twice the switching frequency. The dots mark the winding sense — all four wound the same way, which is what makes the two half cycles oppose each other in the core. The secondary is isolated from the primary; the two returns are separate. Q1 turns amber when the duty cycle per switch is within 10 % of the 50 % overlap limit and red at or past it. The moving dots are the average input and output currents.

10.42µHExample

36–72 V in (a telecom bus), 12 V at 8 A, 150 kHz, 40% maximum duty per switch, 0.5 V diodes, 30% ripple, 50 mV output ripple, 4 primary turns per half on an ETD34 (A_e = 97.1 mm²)

Push-pull power stage (CCM)

V_o = 2·D·V_in·(N_s/N_p) − V_F    so N_s/N_p = (V_o + V_F) ÷ (2·V_in,min·D_max)
L_o = (V_o + V_F)(1 − 2D) ÷ (2·f·ΔI)    C_o = ΔI ÷ (16·f·ΔV)
V_switch = 2·V_in,max    V_diode = 2·V_in,max·N_s/N_p
ΔB = V_in·D ÷ (f·N_p·A_e)    B_pk = ΔB/2    (bipolar: the core works both quadrants)

D: duty cycle of ONE switch, below 0.5. The output stage sees 2D, which is why this is a buck in disguise
1 – 2D: the dead time, in which neither switch conducts. It is what stops the two halves shorting the primary
2 f: the ripple frequency at the output inductor and capacitor: both halves feed the same rectifier
delta B: peak-to-peak flux swing. Push-pull uses the whole B-H loop, so there is no DC bias to spare

Worked example

36–72 V in (a telecom bus), 12 V at 8 A, 150 kHz, 40% maximum duty per switch, 0.5 V diodes, 30% ripple, 50 mV output ripple, 4 primary turns per half on an ETD34 (A_e = 97.1 mm²)
N_s/N_p = 12.5 ÷ (2 × 36 × 0.40) = 0.4340, so N_p : N_s = 2.304 : 1
At 72 V the duty per switch falls to 20.0%, leaving 60.0% dead time; at 36 V it is 40% and 20.0%
L_o = 12.5 × (1 − 0.4) ÷ (2 × 150,000 × 2.4) = 10.42 µH → 12 µH (E12)
C_o = 2.4 ÷ (16 × 150,000 × 0.050) = 20 µF, with an ESR under 20.83 mΩ
Switches stand at 2 × 72 = 144 V; the output diodes at 2 × 72 × 0.4340 = 62.5 V
Volt-seconds per half cycle = 36 × 0.40 ÷ 150,000 = 96 µV·s, so ΔB = 247.2 mT and B_pk = 123.6 mT — 266.4 mT under the 390 mT limit
A 1% volt-second mismatch adds 2.472 mT every cycle, so that headroom is gone in 108 cycles — 718.6 µs. Nothing passive fixes that; current-mode control does

Push-pull against the two other isolated topologies this site covers

Push-pull and the forward converter carry the same switch stress, but push-pull gets twice the core use and twice the output ripple frequency for it, which is why it wins at low input voltages and high current. The reason to avoid it is the last row.
	Push-pull	Forward (1:1 reset)	Flyback
Switches	2, both referenced to the input return	1	1
Switch voltage stress	2 × Vin,max	2 × Vin,max	Vin,max + reflected Vout
Duty limit	below 50% per switch	below 50%	no hard limit
Core use	both quadrants of the B-H loop	one quadrant	one quadrant, gapped
Output inductor	needed, ripples at 2 × f	needed, ripples at f	none
Failure mode it is known for	staircase saturation	core fails to reset	leakage spike on the switch

What sets what

The last row is worth reading twice. Because the controller holds Vin × D constant to keep the output constant, the volt-seconds per half cycle — and therefore the flux swing — do not change across the input range at all. This page asserts that identity rather than assuming it.
Quantity	Set by	Worst case at
Turns ratio	Vin,min and the maximum duty	minimum input
Output inductor ripple	(Vo + Vf)(1 − 2D) ÷ (2·f·L)	maximum input
Output capacitor ripple	ΔI ÷ (16·f·C), plus ESR × ΔI	maximum input
Switch voltage	2 × Vin, plus the leakage spike	maximum input
Switch current	reflected load plus half the inductor ripple	minimum input
Flux swing	Vin × D ÷ (f·Np·Ae) — constant across the line	everywhere equally

A buck with a transformer, and the one thing that goes wrong

Two switches sit at the ends of a centre-tapped primary whose centre goes to the input. They conduct alternately, each for less than half the period, so the transformer sees a symmetrical square wave of ±V_in across each half. The centre-tapped secondary rectifies both halves into the same output inductor, which therefore ripples at twice the switching frequency. Volt-second balance on that inductor gives V_o = 2·D·V_in·N_s/N_p − V_F: a buck converter with 2D where D would be. Every output-stage formula on this page is the buck designer‘s with that substitution and 2f in place of f, and all of them were checked here against a simulation of the switching waveform rather than against each other.

The stress that defines it. While one switch is on, its half of the primary has V_in across it — and so, by transformer action, does the other half, with the opposite sign. The off switch therefore stands at 2·V_in, before any leakage-inductance spike. That is the whole case against push-pull: at a 400 V rectified mains input it would need 800 V switches, which is why push-pull is a low-voltage-input topology (battery, telecom bus, 12–72 V) and a half-bridge or full-bridge is what gets used off the mains. It is also why the dead time is not optional: if both switches are on together the primary is shorted through both halves and the only thing limiting the current is the winding resistance.

Staircase saturation, and why current-mode control. The two half cycles are supposed to apply equal and opposite volt-seconds, so the flux ends each full cycle where it started. They never do exactly. One switch has a slightly lower on-resistance, one gate drive is a few tens of nanoseconds longer, the two primary halves have slightly different leakage. Whatever flux the mismatch leaves behind is carried into the next cycle and added to, so the operating point walks up the B-H loop a step at a time — a staircase — until the core saturates, the primary inductance collapses and the switch current is limited only by resistance. On this page’s own example a 1% mismatch uses up the core’s entire flux headroom in about half a millisecond. A voltage-mode loop cannot see it, because the output voltage is still correct all the way up. Peak current-mode control can: the mismatch appears directly as a difference in primary current between the two half cycles, and a current-mode comparator terminates whichever pulse reaches the threshold first, which is by construction the longer one. That is why push-pull converters are normally built round a current-mode controller, and why a DC blocking capacitor in series with the primary — the cure used in a half-bridge — is awkward here, since there is no single winding both halves share.

What this page leaves out. Leakage inductance and the spike it puts on the switch at turn-off (size a clamp with the RC snubber calculator), the magnetising current, the transformer’s copper and core losses (the SMPS transformer calculator sizes the core and the wire), and the control loop. Switch losses go through the MOSFET loss calculator and the rectifiers through the diode power loss calculator.

Frequently asked questions

Why is a push-pull converter limited to 50% duty per switch?

Because the two switches sit across the two halves of one winding. If they overlap even briefly, the primary is shorted through both halves and only the winding resistance limits the current. The 1 − 2D left over is the dead time, and it has to be long enough to cover the gate-drive delay and the controller’s own tolerance.

What voltage do the switches see in a push-pull converter?

2 × Vin,max, plus the leakage-inductance spike. When one switch is on, the other half of the primary has the same voltage induced across it with the opposite sign, so the off switch stands at twice the input. For this page’s 72 V maximum that is 144 V before any spike, and it is the reason push-pull is used at low input voltages and a bridge topology off the mains.

What is staircase saturation in a push-pull transformer?

The two half cycles never apply exactly equal volt-seconds — the switches, the gate drives and the two primary halves all differ slightly — so a little flux is left over at the end of every cycle and added to the next. The operating point walks up the B-H loop until the core saturates. The output voltage is correct the whole way, so a voltage-mode loop never sees it coming.

Why do push-pull converters use current-mode control?

Because a volt-second mismatch shows up immediately as a difference in primary current between the two half cycles, and peak current-mode control terminates whichever pulse hits the current threshold first. That is automatically the longer one, so the imbalance is corrected cycle by cycle before the flux can walk. Cycle-by-cycle current limiting and the flux decay allowed by the dead time help too, but current-mode control is the one that fixes the cause.

How do you size the output inductor of a push-pull converter?

L = (Vo + Vf)(1 − 2D) ÷ (2·f·ΔI), at the maximum input where D is smallest and the ripple largest. The 2 in the denominator is there because both halves of the transformer feed the same rectifier, so the inductor ripples at twice the switching frequency.

Related calculators

References

Texas Instruments, How to prevent transformer saturation in push-pull converters, application note SLYT813 (Analog Design Journal). States the cause — “if there is a mismatch between the two phases of operation … the flux buildup in the transformer in one cycle is not fully canceled in the other” — and the three mitigations: negative feedback through the FET on-resistance, cycle-by-cycle current limiting, and flux decay during the dead time, with the rule that the dead-time percentage must be at least the flux-mismatch percentage. Used for this page’s flux-walk section.
Texas Instruments (Unitrode), UC1846/UC3846 Current Mode PWM Controller data sheet, and design note UC3846, UC3856 and UCC3806 Push Pull PWM Current Mode Control ICs (DN-45). The push-pull current-mode controller family whose alternating outputs and cycle-by-cycle current comparator are the standard answer to the flux-imbalance problem.
Erickson RW, Maksimović D. Fundamentals of Power Electronics, 3rd ed. Springer, 2020. Ch. 6 (transformer-isolated converters, the push-pull among them) and Ch. 2 (inductor volt-second and capacitor charge balance, which is where every output-stage formula here comes from — this page checks them against a simulation rather than quoting them).
Mohan N, Undeland TM, Robbins WP. Power Electronics: Converters, Applications, and Design, 3rd ed. Wiley, 2003. Ch. 10, push-pull converter: the 2·V_in switch stress and the flux-imbalance problem.
IEC 60063:2015. Preferred number series for resistors and capacitors. The E6 and E12 series used for the suggested standard parts.