Logic Level Compatibility and Level Shifter Calculator
Logic Level Compatibility and Level Shifter Calculator
Whether one device can drive another directly, in both directions, from the four numbers on their datasheets — with the noise margins as the voltages they actually are, the absolute-maximum check that decides it whatever the margins say, and the resistive divider or MOSFET shifter you need when it cannot.
Logic level compatibility
a 5 V 74HC output driving a 3.3 V LVCMOS input directly: Vᴼʜ 4.4 V, Vᴼʟ 0.33 V into Vᴵʜ 2.0 V, Vᴵʟ 0.8 V, the 3.3 V pin not 5 V tolerant
Margins, the divider and the pass FET
divider: R2 = R1 · Vtarget ÷ (VOH − Vtarget), level = VOH · R2/(R1+R2), tr = 2.2 · (R1∥R2) · C
pass FET: gate at the LOWER rail, so it conducts while the low side is pulled down and is off when both sides are high
- V OH, V OL
- the driving pin’s output levels, each specified at a stated current — read them at the current you will actually draw
- V IH, V IL
- the receiving pin’s thresholds. CMOS states them as 0.7 and 0.3 of its own supply; TTL-compatible inputs as fixed 2.0 and 0.8 V
- absolute max
- usually V DD + 0.3 V unless the pin is specified as tolerant. Exceeding it forward-biases the input protection diode into the supply
- 2.2
- ln 9 — the 10% to 90% rise of an RC node in time constants
Worked example
a 5 V 74HC output driving a 3.3 V LVCMOS input directly: Vᴼʜ 4.4 V, Vᴼʟ 0.33 V into Vᴵʜ 2.0 V, Vᴵʟ 0.8 V, the 3.3 V pin not 5 V tolerant
High margin: 4.4 − 2.0 = 2.40 V. Low margin: 0.8 − 0.33 = 0.47 V, which is the worse of the two and the headline
Both are positive, so the LEVELS are fine — and the connection is still wrong: 4.4 V into a pin whose absolute maximum is 3.3 + 0.3 = 3.6 V is 0.80 V over
A divider from 10 kΩ needs R2 = 10 kΩ × 3.3 ÷ (4.4 − 3.3) = 30.00 kΩ, so 30 kΩ from E24, giving 3.30 V at the pin
That divider's Thévenin resistance is 7,500 Ω, so into 15 pF it rises in 247.5 ns — fine for SPI at a few MHz, not for 50
The other direction fails outright: the 3.3 V part's 3.1 V Vᴼʜ against the 5 V part's 3.5 V Vᴵʜ is a margin of -0.40 V
The level families, as their standards define them
| Family | Vᴰᴰ | Vᴼʜ | Vᴼʟ | Vᴵʜ | Vᴵʟ | What it means in practice |
|---|---|---|---|---|---|---|
| 5 V CMOS (74HC at 5 V) | 5.0 | 4.4 | 0.33 | 3.5 | 1.5 | Vᴵʜ is 0.7 Vᴰᴰ and Vᴵʟ is 0.3 Vᴰᴰ, so a 3.3 V output cannot reach it. |
| 5 V TTL-compatible (74HCT, 74LS) | 5.0 | 4.4 | 0.33 | 2.0 | 0.8 | The TTL thresholds are fixed voltages, not fractions of the rail — which is why a 3.3 V part CAN drive an HCT input. |
| 3.3 V LVCMOS (JESD8-C) | 3.3 | 3.1 | 0.2 | 2.0 | 0.8 | Vᴼʜ is Vᴰᴰ − 0.2 V at 100 µA; the thresholds are the same 2.0 and 0.8 V as LVTTL. |
| 3.3 V LVTTL (JESD8-C) | 3.3 | 2.4 | 0.4 | 2.0 | 0.8 | Same thresholds, but Vᴼʜ is only 2.4 V at 2 mA — so the margin into another LVTTL input is 0.4 V. |
| 2.5 V (JESD8-5) | 2.5 | 2.0 | 0.4 | 1.7 | 0.7 | Will not drive a 3.3 V LVCMOS input that wants 2.0 V. |
| 1.8 V (JESD8-7) | 1.8 | 1.35 | 0.45 | 1.17 | 0.63 | Vᴵʜ is 0.65 Vᴰᴰ. Below 2.5 V, everything needs a translator. |
Four numbers decide it, and a fifth overrules them
Whether one chip can drive another is settled by four numbers and nothing else. The driver’s VOH must clear the receiver’s VIH, and the driver’s VOL must stay below the receiver’s VIL. The two differences are the noise margins, and they are voltages, not percentages: quote them in millivolts and the argument usually ends. The fifth number overrules all four — the receiving pin’s absolute maximum input voltage, normally its own supply plus 0.3 V, because above that the input protection diode conducts into the receiver’s rail. A connection can have handsome margins and still be wrong.
The two cases people meet. 5 V driving 3.3 V: the margins are fine and the absolute maximum is not, so the level has to come down. 3.3 V driving 5 V CMOS: the absolute maximum is fine and the high margin is negative, because a 5 V CMOS input wants 0.7 × 5 = 3.5 V and a 3.3 V part cannot produce it. The exception worth remembering is a TTL-compatible input — 74HCT, 74LS, and most 5 V microcontroller pins specified at a fixed 2.0 V — which a 3.3 V output drives with over a volt to spare. Check which kind of input you have before you buy a translator.
Down-shifting with two resistors. A divider is the cheapest shifter there is and it has exactly one drawback: it is an RC low-pass with the capacitance of the track and the pin. The rise time is 2.2 × (R1∥R2) × C, so a 10 kΩ divider into 15 pF and the 10 kΩ divider in the example has a Thévenin resistance of 7.5 kΩ, so into 15 pF it takes about 250 ns to get there — call it a megabit per second. Ten times smaller resistors are ten times faster and draw ten times the current whenever the line is high. It also only works one way, and only from a push-pull output: on an open-drain bus it fights the pull-up. For the pull-up arithmetic on such a bus — the minimum set by the sink current and the maximum set by the rise time — the I²C pull-up resistor calculator does the whole window properly, and the same rise-time limit applies here.
The MOSFET shifter, and when it is the right answer. One N-channel enhancement MOSFET per line, gate tied to the LOWER supply, source on the low-voltage side and drain on the high-voltage side, with a pull-up on each side to its own rail. Philips’ AN97055 sets out the three states: both sides idle high and the FET is off, because VGS is zero; the low side pulls down and VGS rises to the lower rail, so the FET conducts and drags the high side down with it; the high side pulls down and the drain-substrate diode starts the job before the FET finishes it. It is bidirectional with no direction pin, which is why every I²C bus crossing a voltage boundary uses it. Two conditions: both sides must be open-drain, and the worst-case VGS(th) must be comfortably below the lower rail — a BSS138 is specified up to 1.5 V, which is fine from 3.3 V and not fine from 1.8 V.
And when you need none of it. If the receiving pin is specified as tolerant of the higher rail — and many 3.3 V microcontrollers specify most of their pins that way, though rarely the analogue ones — then a 5 V push-pull output connects straight to it, provided the margins hold. That is a datasheet fact about a particular pin, not a property of the family, and it is the one thing on this page worth looking up rather than assuming. For the interface whose timing this decides, the UART baud rate calculator; for driving an LED or a load from the pin instead of another input, the LED series resistor calculator and the BJT base resistor calculator.
Frequently asked questions
Can a 5 V output drive a 3.3 V input directly?
Only if that input is specified as 5 V tolerant. The logic levels are fine — 4.4 V clears a 2.0 V threshold easily — but 4.4 V on a pin whose absolute maximum is 3.6 V forward-biases its protection diode into the 3.3 V rail. Some parts survive it for years and then do not.
Can a 3.3 V output drive a 5 V input?
It depends on the input’s threshold, not on the supply. A 5 V TTL-compatible input (74HCT, 74LS, most 5 V microcontroller pins) wants 2.0 V and is driven with margin to spare. A 5 V CMOS input (74HC) wants 0.7 × 5 = 3.5 V, which a 3.3 V part cannot reach, so it needs a translator or an HCT buffer.
What is a noise margin?
The voltage between what the driver guarantees and what the receiver requires: V_OH − V_IH for the high state and V_IL − V_OL for the low one. Both must be positive, and the smaller of the two is what you have. A few hundred millivolts is comfortable on a short board track; less than 200 mV is asking for trouble once ground offset and switching noise are added.
How fast can a resistive level shifter go?
It is an RC low-pass: the 10-90% rise time is 2.2 × (R1 in parallel with R2) × the load capacitance. A 10 kΩ and 30 kΩ divider is 7.5 kΩ, which into 15 pF is about 250 ns — a megabit or so; ten times smaller resistors get you ten times that and draw ten times the current. Above that, use a MOSFET shifter or a dedicated translator.
When should I use a MOSFET level shifter instead of a divider?
Whenever the line is bidirectional or open-drain — I²C, a one-wire bus, any shared line. A divider only shifts one way and only from a push-pull output. The MOSFET circuit works in both directions with no control signal, at the cost of a pull-up on each side and the rise time those pull-ups give.
Why does my V_OH not match the datasheet?
Because V_OH is specified at a stated output current, and it falls as you draw more. A 74HC part guarantees 4.4 V at 4 mA from a 4.5 V supply, but only about V_DD − 0.1 V at a few microamps. Read the number at the current your circuit actually pulls.
Related calculators
References
- JEDEC. JESD8-C, Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits (June 2006, revising JESD8-B). LVTTL and LVCMOS both take VIH = 2.0 V minimum and VIL = 0.8 V maximum; LVTTL’s VOH is 2.4 V at −2 mA and VOL 0.4 V at 2 mA, while LVCMOS’s are VDD − 0.2 V and 0.2 V at ±100 µA. Those are the figures in the 3.3 V rows of the table above.
- Analog Devices. MT-098 Tutorial: Low Voltage Logic Interfacing. Defines VOH, VOL, VIH and VIL and the margins between them, lists the JEDEC levels for 5 V, 3.3 V, 2.5 V and 1.8 V logic, and states the 5 V-into-LVTTL case plainly: “the 5 V TTL high level is too high for the LVTTL to handle (> 3.3 V). This could cause permanent damage to the LVTTL chip.”
- Schutte H. AN97055: Bi-directional level shifter for I²C-bus and other systems. Philips Semiconductors, 4 August 1997. The single N-channel enhancement MOSFET per line, gate to the lower supply, source on the low-voltage side, and the three states of operation described in the body above.
- NXP / Nexperia. AN10441: Level shifting techniques in I²C-bus design, rev. 2, 10 February 2020. The same MOSFET shifter as applied to I²C, for Standard-mode and Fast-mode buses; explicitly not intended for Hs-mode.