PCB Propagation Delay and Length Matching Calculator
PCB Propagation Delay and Length Matching Calculator
How long a signal takes to get down a trace, on an outer layer or an inner one: the delay per millimetre from the stack-up, the delay along the whole trace, the electrical length in degrees, the skew between two traces of different length, and the matching tolerance a skew budget leaves you — plus the length at which the trace starts behaving as a transmission line at all, which depends on the rise time and not on the clock.
Propagation delay and skew
a 100 mm microstrip 0.25 mm wide over 0.2 mm of FR-4 (εᵣ 4.3), 1 oz copper, matched against an 85 mm trace with a 10 ps budget and a 500 ps edge
Delay, skew and critical length
stripline: εeff = εr; microstrip: εeff = (εr+1)/2 + (εr−1)/2 · (1 + 12h/w)−1/2 (Hammerstad, with the copper-thickness correction)
matching tolerance = skew budget ÷ tpd critical length = tr ÷ (6 tpd) electrical length = 360° × length ÷ λg
- eps eff
- the permittivity the wave actually sees. Between 1 and ε r for a microstrip because part of the field is in air; exactly ε r for a stripline
- c
- 299,792,458 m/s — 3.336 ps per millimetre in free space
- t r
- the 10–90% rise time of the EDGE. The clock frequency does not appear in the critical-length rule at all
- 1/6
- the convention used here for “electrically long”. Johnson puts the threshold people actually use at between a tenth and a third of the rising edge’s length, and simulates anything longer than a sixth
Worked example
a 100 mm microstrip 0.25 mm wide over 0.2 mm of FR-4 (εᵣ 4.3), 1 oz copper, matched against an 85 mm trace with a 10 ps budget and a 500 ps edge
w/h = 1.250, so Hammerstad's ε_eff is 3.1836 — well under 4.3, because part of the field is in the air above the trace
tpd = √3.1836 ÷ c = 5.9517 ps/mm (151.2 ps per inch), which is 56.0% of the speed of light
Over 100 mm that is 595.2 ps; the 85 mm trace takes 505.9 ps, so the pair is 89.3 ps apart — nine times the budget
To hold 10 ps the two lengths must agree within 10 ÷ 5.9517 = ±1.68 mm
The same trace buried as a stripline would take 691.7 ps — 16.2% slower, so a bus that changes layers halfway is not matched by length alone
With a 500 ps edge the critical length is 500 ÷ (6 × 5.9517) = 14.0 mm, so at 100 mm this trace is a transmission line and wants terminating
How fast a signal travels, by what surrounds it
| Medium | ε_eff | Delay per mm | Per inch | Speed | Length per ns | Notes |
|---|---|---|---|---|---|---|
| Microstrip on FR-4, εᵣ 4.3 (this page’s default geometry) | 3.1836 | 5.9517 ps/mm | 151.2 ps/in | 56.0% | 168.0 mm | Part of the field is in the air above the trace, so the wave sees less than 4.3 and runs faster. |
| Stripline on the same FR-4 | 4.3000 | 6.9169 ps/mm | 175.7 ps/in | 48.2% | 144.6 mm | Every field line is in the laminate, so ε_eff is εᵣ exactly — about 15% slower than the microstrip beside it. |
| Microstrip on Rogers 4350B, εᵣ 3.48 | 2.6422 | 5.4220 ps/mm | 137.7 ps/in | 61.5% | 184.4 mm | A lower-loss laminate, and a faster one. |
| Stripline on Rogers 4350B | 3.4800 | 6.2226 ps/mm | 158.1 ps/in | 53.6% | 160.7 mm | Still slower than the microstrip above it. |
| Coaxial cable with solid PTFE, εᵣ 2.1 | 2.1000 | 4.8338 ps/mm | 122.8 ps/in | 69.0% | 206.9 mm | The classic 69% velocity factor. |
| Free space | 1.0000 | 3.3356 ps/mm | 84.7 ps/in | 100.0% | 299.8 mm | 3.336 ps per millimetre, and nothing on a board gets near it. |
Delay, skew, and what “long” means
A signal on a board travels at c divided by the square root of the permittivity it passes through, and that is the entire calculation. The impedance of the trace does not appear: a 50 Ω line and a 90 Ω line on the same layer of the same board have the same delay per millimetre. What changes it is what surrounds the copper. A stripline is buried in laminate, so its field sees εᵣ and nothing else. A microstrip has air above it, so part of its field runs through ε = 1 and the wave sees an average — an effective permittivity between 1 and εᵣ, which is why an outer-layer trace is about 15% faster than an inner-layer one on the same FR-4. That is the practical consequence worth remembering, and it is why a length-matched bus must not change layers halfway.
Length matching is just this arithmetic run backwards. Skew is the delay difference, so it is tpd times the length difference. On FR-4 microstrip that is about 6 ps per millimetre, so a 10 ps budget means holding the two lengths to within about 1.7 mm of each other — which is why serpentine routing exists and why the tolerance is quoted in millimetres on the layout and in picoseconds in the specification. Two cautions. Serpentines are not free: the parallel sections couple to each other and a tightly wound one is electrically shorter than its physical length, so keep the spacing between the turns at three times the trace-to-plane height or more. And matching by length only matches delay if both traces run in the same stack-up, at the same width, over unbroken reference planes.
When does a trace become a transmission line? Not at a frequency — at a RISE TIME. If a reflection from the far end gets back before the edge has finished rising, the driver never sees a distinct echo and the line behaves as a lumped wire. If it arrives afterwards, the receiver sees a step, a pause and then a reflection, and you have to terminate. The threshold is therefore a length: rise time divided by some multiple of the delay per unit length. This page uses one sixth of the rising edge’s length, the figure Howard Johnson gives as the point beyond which he simulates everything; he puts the threshold people actually use at anywhere from a tenth to a third, depending on how much ringing the circuit tolerates. With a 500 ps edge on FR-4 microstrip, that is 14 mm. Note what is absent from the calculation: the clock frequency. A 1 MHz clock from a modern FPGA with a 200 ps edge needs the same treatment as a 500 MHz one, because it is the edge that carries the high-frequency content.
How good these numbers are. The delay constant is only as good as εᵣ, and εᵣ is not a constant: FR-4’s falls with frequency, varies by a few per cent between resin systems, and differs between the core and the prepreg in the same stack-up. A 5% error in εᵣ is a 2.5% error in delay, which on a 500 ps trace is 12 ps — larger than many skew budgets. So this page is for design, and the fabricator’s stack-up figures or a measured time-domain reflectometry trace are for verification. The microstrip ε_eff relation was checked here against a finite-volume solve of the actual cross-section, written from scratch, and agrees within 1.2%; the delay itself was checked against a step propagating down a simulated LC ladder, which reproduces √ε_eff ÷ c without being told it.
For the impedance of the same geometry — which you need as well, and which does depend on the width — see the microstrip impedance calculator and the stripline impedance calculator, whose delay figures this page reproduces exactly; for a matched pair, the differential pair impedance calculator. For the via that takes the signal between layers, the PCB via calculator, and for what the same trace costs in millivolts rather than picoseconds, the PCB trace resistance calculator.
Frequently asked questions
What is the propagation delay of a PCB trace?
About 6 ps per millimetre (150 ps per inch) for a microstrip on FR-4, and about 6.9 ps/mm (176 ps/inch) for a stripline on the same board. The formula is √ε_eff ÷ c: a stripline’s ε_eff is ε_r itself, while a microstrip’s is lower because part of its field is in the air above the trace.
Why is a stripline slower than a microstrip?
Because all of its field is in the laminate. A microstrip’s field is shared between the board and the air above it, so the wave sees an average permittivity lower than ε_r and travels faster. On FR-4 the difference is about 15%, which is more than most length-matching budgets.
How closely do I have to match trace lengths?
Divide the skew budget by the delay per unit length. On FR-4 microstrip at 6 ps/mm, a 10 ps budget is ±1.7 mm and a 50 ps budget is ±8.4 mm. The same budget on an inner layer is slightly tighter in millimetres, because a stripline is slower.
When does a trace need termination?
When it is electrically long for the signal’s RISE TIME, not for its frequency. The usual rule is a critical length of one sixth of the rising edge’s physical length: with a 500 ps edge on FR-4 microstrip that is about 14 mm. Slower edges tolerate longer traces; a faster part on the same clock can change the answer.
Does trace impedance change the delay?
No. Delay per unit length is √ε_eff ÷ c, and the width that sets the impedance only enters through its small effect on ε_eff for a microstrip. A 50 Ω and a 90 Ω trace on the same layer arrive at practically the same time.
Does a serpentine really add the delay its length suggests?
Not quite. The parallel runs couple to each other, which makes a tightly wound serpentine electrically shorter than its physical length — typically a few per cent. Keep the gap between turns at three or more times the height to the reference plane and the error stays small.
Related calculators
References
- Johnson HW, Graham M. High-Speed Digital Design: A Handbook of Black Magic. Prentice Hall, 1993. The rise-time criterion for a transmission line. On his own site Johnson states it directly: “the critical line length beyond which many people use terminators varies from about 1/10 to 1/3 the length of the rising edge”, and “I generally simulate all lines longer than about 1/6 of the risetime” — which is the convention this page uses.
- Hammerstad EO, Jensen Ø. Accurate Models for Microstrip Computer-Aided Design. IEEE MTT-S International Microwave Symposium Digest, 1980. The ε_eff relation used here. It is the same one this site’s microstrip impedance record computes, and this page reproduces that record’s worked example exactly — ε_eff 3.2605 and 6.0231 ps/mm on a 3 mm trace over 1.6 mm FR-4 — as an assertion in the test suite.
- Cohn SB / IPC-2141A. The stripline case needs no fit at all: with laminate on every side the mode is TEM and ε_eff is ε_r exactly, so t_pd = √ε_r ÷ c. This site’s stripline record states the same 6.9169 ps/mm at ε_r 4.3, and that figure is asserted here too.
- Bogatin E. Signal and Power Integrity — Simplified. Prentice Hall. The standard treatment of delay, effective permittivity and length matching for board designers. Cited from the published literature rather than fetched for this build: the numerical content of this page rests on the two checks described above, not on this reference.