PCB Via Current Calculator
PCB Via Current Calculator
How much current a plated via barrel can carry for a temperature rise you choose, from its finished hole diameter, plating thickness and the board’s thickness — with the barrel’s copper cross-section, its resistance and voltage drop, and, for a thermal via array, the thermal resistance the array actually gives.
Via current capacity
one 0.3 mm finished via with 25 µm of barrel plating through a 1.6 mm board, 10 °C rise, treated as an external conductor
The barrel, unrolled
I = k · ΔT0.44 · A0.725 (A in mil², k = 0.048 external, 0.024 internal — IPC-2221’s conductor relation)
R = ρT · L ÷ A, ρT = 0.017241 (1 + 0.00393(T − 20)) Ω·mm²/m
θ = L ÷ (kcuA) in parallel with L ÷ (kfillAhole), kcu = 385 W/(m·K)
- d, t
- finished hole diameter and the plating thickness in the barrel — 20 µm for IPC-6012 Class 2, 25 µm for Class 3
- L
- the barrel’s length: the board thickness for a through via, the layer separation for a blind or buried one
- k
- IPC-2221’s constant. There is no via-specific value; this page lets you choose which conductor case to borrow
- theta
- thermal resistance along the barrel. An array of n vias divides it by n, and a plane at the far end is assumed
Worked example
one 0.3 mm finished via with 25 µm of barrel plating through a 1.6 mm board, 10 °C rise, treated as an external conductor
Barrel copper: π × 0.025 × (0.3 + 0.025) = 0.02553 mm², which is 39.56 mil² — the same as a trace 1.021 mm wide and 25 µm thick
IPC-2221: I = 0.048 × 100.44 × 39.560.725 = 1.902 A
Resistance at 35 °C: ρ = 0.018257 Ω·mm²/m, so R = 0.018257 × 0.0016 ÷ 0.02553 = 1.144 mΩ — at 1 A that is 1.144 mV of drop
As a thermal path the same barrel is 1.6 mm ÷ (385 W/m·K × 0.02553 mm²) = 162.8 K/W; an open hole adds almost nothing, so the via is 162.8 K/W
Nine of them under a thermal pad would be 18.1 K/W, which is the figure worth comparing against the package's own θJC
Common via sizes, through a 1.6 mm board
| Finished hole | Plating | Barrel copper | At 10 °C rise | At 20 °C rise | Resistance | Thermal resistance |
|---|---|---|---|---|---|---|
| 0.20 mm (8 mil) | 20 µm | 13.82 × 10⁻³ mm² | 1.22 A | 1.65 A | 2.113 mΩ | 301 K/W |
| 0.25 mm (10 mil) | 20 µm | 16.96 × 10⁻³ mm² | 1.41 A | 1.92 A | 1.722 mΩ | 245 K/W |
| 0.30 mm (12 mil) | 25 µm | 25.53 × 10⁻³ mm² | 1.90 A | 2.58 A | 1.144 mΩ | 163 K/W |
| 0.40 mm (16 mil) | 25 µm | 33.38 × 10⁻³ mm² | 2.31 A | 3.13 A | 875.1 µΩ | 125 K/W |
| 0.50 mm (20 mil) | 25 µm | 41.23 × 10⁻³ mm² | 2.69 A | 3.65 A | 708.4 µΩ | 101 K/W |
| 0.60 mm (24 mil) | 30 µm | 59.38 × 10⁻³ mm² | 3.51 A | 4.76 A | 492 µΩ | 70 K/W |
| 0.80 mm (31 mil) | 30 µm | 78.23 × 10⁻³ mm² | 4.28 A | 5.81 A | 373.4 µΩ | 53 K/W |
A via is a trace you cannot see the width of
A plated via is a cylinder of copper a few tens of microns thick. Unroll it and it is a flat conductor π(d + t) wide and t thick, and that is not an analogy — the algebra is exact: π((d/2 + t)² − (d/2)²) = π·t·(d + t). A 0.3 mm via with 25 µm of plating unrolls to a trace 1.02 mm wide and 25 µm thick, which is 0.026 mm² of copper, about three quarters of what a 1 mm trace in 1 oz copper gives you. That is the whole model on this page: work out the barrel’s cross-section, then put it through the same IPC-2221 conductor relation the trace width calculator uses, with the same constants.
What IPC actually says about vias, which is nothing. IPC-2221’s conductor charts are measurements of traces on a board surface and inside a laminate. There is no via curve in IPC-2221, and none in IPC-2152 either. Every via current calculator you will find, this one included, applies the trace relation to the barrel’s equivalent cross-section, and the honest description of that is a convention the industry has settled on rather than a standard. It is a defensible convention: a via is short, it is surrounded by laminate that conducts heat better than air along the barrel, and it ends at two pads that act as heatsinks, so the trace relation is generally pessimistic for a via. But when the number matters — a power via array on a converter, a via carrying tens of amperes — the fabricator’s own guidance and a thermal measurement are what decide, not this page.
The resistance is usually the part that matters. A 0.3 mm through via in a 1.6 mm board is about 1.1 mΩ. That sounds negligible and is not: put ten amperes through one and it drops 11 mV and dissipates 114 mW in a volume smaller than a grain of rice. On a buck converter’s ground return, four such vias in parallel are 0.29 mΩ and the same current drops under 3 mV. The rule that follows is simple — always use several, both for the resistance and because plating voids are a real defect mode and a single via is a single point of failure.
Thermal vias are a different calculation with the same geometry. Under a package’s thermal pad the barrel is a heat path, not a current path: θ = L ÷ (k × A) with copper’s 385 W/(m·K). For the 0.3 mm via above that is about 163 K/W, which sounds hopeless until you put twenty-five of them under a QFN and get 6.5 K/W — comparable with the package’s own junction-to-case resistance, which is the point at which adding more stops helping. Fill the barrel with solder and it improves by about a quarter — 163 K/W down to 120 — because the solder’s cross-section is much larger than the copper shell’s even though its conductivity is an eighth of copper’s; a non-conductive epoxy fill changes essentially nothing. What this page does NOT model is the spreading resistance in the plane the vias feed, which is often the real limit: for that, and for the package-to-ambient path as a whole, see the heatsink thermal resistance calculator.
The two limits that catch people out are fabrication limits, not electrical ones. The aspect ratio — board thickness divided by hole diameter — has to stay under about 10:1 for the plating to reach the middle of the barrel evenly, and the plating thickness is set by the fab’s process, not by the surface copper weight you specified: IPC-6012 asks for 20 µm average at Class 2 and 25 µm at Class 3, and that is a minimum, not a target. For the trace that feeds the via, the PCB trace resistance calculator and the trace width page; for the impedance discontinuity the same via causes in a high-speed signal, the propagation delay and length matching calculator.
Frequently asked questions
How much current can a 0.3 mm via carry?
About 1.9 A for a 10 °C rise with 25 µm of barrel plating, by the IPC-2221 relation applied to the barrel’s cross-section, or about 2.6 A if you allow 20 °C. Those are per via: the usual design move is to use four or more in parallel, which also cuts the resistance.
Does IPC-2221 have a rule for via current?
No. Its charts are measurements of traces, and neither IPC-2221 nor IPC-2152 publishes a via curve. What every calculator does — this one included — is compute the barrel’s copper cross-section and put it through the trace relation. It is a convention, and the fabricator’s own guidance supersedes it.
How do I work out a via’s copper cross-section?
A = π × t × (d + t), where d is the finished hole diameter and t the plating thickness in the barrel. For a 0.3 mm hole with 25 µm of plating that is 0.0255 mm². It is exactly the same as the annulus formula π((d/2+t)² − (d/2)²) — the barrel unrolled is a trace π(d + t) wide.
How many thermal vias do I need?
Work out one via’s thermal resistance — L ÷ (385 × A), about 163 K/W for a 0.3 mm via in a 1.6 mm board — and divide by the number, because they are in parallel. Keep adding until the array’s figure is well below the package’s own junction-to-case resistance; past that the spreading resistance in the plane, which this page does not model, becomes the limit.
What plating thickness should I assume?
20 µm if you are building to IPC-6012 Class 2 and 25 µm for Class 3 — both are minimum averages, not typical values. Do not take it from the surface copper weight: barrel plating is a separate process step, and a 1 oz board does not mean 35 µm in the hole.
Does filling the via help?
For heat, a little — solder fill adds a parallel path whose cross-section is much bigger than the thin copper shell, and it takes the 0.3 mm via above from 163 K/W to 120, about a quarter off. A non-conductive epoxy fill is worth almost nothing thermally. For current, no: solder is roughly a tenth as conductive as copper electrically, so the barrel still carries essentially all of it.
Related calculators
References
- IPC-2221B. Generic Standard on Printed Board Design, IPC, 2012, §6.2 — the conductor current-carrying charts and the curve fit I = k·ΔT0.44·A0.725 with k = 0.048 external and 0.024 internal. The standard is a paid document and was not read for this page; the relation, its constants and its range (to 35 A, 10 to 100 °C) are the same ones already stored in this site’s trace width record, which is where they were taken from, and they were checked here by inverting the relation numerically.
- IPC-2152. Standard for Determining Current Carrying Capacity in Printed Board Design, IPC, 2009. Supersedes the IPC-2221 charts for traces. Like IPC-2221 it contains no via-specific curve, so the adaptation above is not made redundant by it — but for a design where the number matters, its charts and the fabricator’s guidance are the authority.
- Sierra Circuits. Design a via with current-carrying capacity. States the same general relation I = k·ΔT0.44·A0.725 with k = 0.024 internal and 0.048 external, and describes the barrel as a cylinder of copper whose circumference plays the part of a trace’s width — the unrolling this page makes exact.
- IPC-6012. Qualification and Performance Specification for Rigid Printed Boards. Minimum average copper in a plated hole: 20 µm (0.8 mil) for Class 2 and 25 µm (1.0 mil) for Class 3. Taken from a published summary of the standard’s plating tables rather than from the standard itself, which is a paid document.
- Sierra Circuits. How thermal vias enhance heat dissipation in PCBs. Copper’s thermal conductivity as ≈385 W/(m·K), thermal via diameters of 0.2 to 0.4 mm and a via-to-via pitch of 1 to 1.2 mm to stop solder wicking off the pad, with the aspect ratio kept under 10:1.