UART Baud Rate Error Calculator
UART Baud Rate Error Calculator
The divisor your peripheral clock and target baud rate actually produce, the baud rate that comes back out of it, the error in per cent — and the part that decides whether the link works: how far the sampling point has drifted by the stop bit, and how much error the receiver at the other end can take.
UART baud rate error
a 16 MHz peripheral clock asked for 115,200 baud, 8N1, oversampling by 16 with an integer divisor
Divisor, error and the receiver’s window
the stop bit is sampled (D + 1.5) bit times after the start edge, so an ideal receiver tolerates ±0.5/(D + 1.5)
a real one votes on samples SF, SF+1, SF+2 of S: Rslow = (D+1)S ÷ (S − 1 + D·S + SF), Rfast = (D+2)S ÷ ((D+1)S + SM)
- S
- oversampling ratio — 16 normally, 8 in double-speed or OVER8 mode
- K
- 1 for an integer divisor, 16 or 8 for a fractional baud generator
- D
- data bits plus the parity bit — 8 for 8N1. The start bit is counted separately and the stop bit is the one being sampled
- S F, S M
- the first and middle of the three samples the receiver majority-votes: 8 and 9 of 16, or 4 and 5 of 8
- R
- the incoming bit rate as a fraction of the receiver’s own. Subtract 1 and it is the tolerance in per cent
Worked example
a 16 MHz peripheral clock asked for 115,200 baud, 8N1, oversampling by 16 with an integer divisor
The exact divisor is 16 MHz ÷ (16 × 115,200) = 8.6806, and the hardware can only load 9
That gives 111,111.11 baud, an error of -3.549% (UBRR = 8)
8N1 means D = 8, so the stop bit is sampled 9.5 bit times after the start edge: at this error the sampling point has drifted 33.7% of a bit
An ideal receiver would tolerate ±5.26%; a 16× majority-voting one tolerates -4.64% to +4.58%
So it works against an accurate partner, with 1.03% left for the other end — less than the ±2.0% each device is normally allowed
Double speed (U2X, 8× oversampling) on the same clock gives a divisor of 17 and an error of +2.124%, which is why the Arduino core uses it
What the common clocks do at 9600 and 115200 baud
| Peripheral clock | 9600, 16× | 9600, 8× | 115200, 16× | 115200, 8× | Notes |
|---|---|---|---|---|---|
| 8 MHz | 0.16% | 0.16% | 8.51% | -3.55% | The commonest failure on this list: no divisor lands near 115200. |
| 11.0592 MHz | 0.00% | 0.00% | 0.00% | 0.00% | A “UART crystal” — 11.0592 MHz is 115200 × 96, so every standard rate is exact. |
| 12 MHz | 0.16% | 0.16% | -6.99% | 0.16% | The usual USB crystal. Fine at 9600, hopeless at 115200. |
| 16 MHz | 0.16% | 0.16% | -3.55% | 2.12% | The Arduino Uno’s clock. 115200 is 3.55% out at 16×, which is why the Arduino core turns on double speed (U2X). |
| 14.7456 MHz | 0.00% | 0.00% | 0.00% | 0.00% | 115200 × 128. Exact everywhere, and still cheap. |
| 20 MHz | 0.16% | 0.16% | -1.36% | -1.36% | A fast AVR clock; the round number is the problem. |
| 48 MHz | -0.16% | 0.00% | 0.16% | 0.16% | A typical USB-capable Cortex-M0 clock. |
| 72 MHz | -0.05% | -0.05% | 0.16% | 0.16% | The classic STM32F1 system clock. |
Why the error matters more than it looks
A UART has no clock line. The receiver finds the start edge, then counts on its own clock to the middle of each bit and samples there. Nothing resynchronises it until the next start edge, so a difference in bit rate between the two ends accumulates across the whole character and is at its largest at the last bit sampled — the stop bit.
Where the tolerance comes from. For 8N1 the stop bit is sampled 9.5 bit times after the start edge. If the receiver’s bit period differs from the transmitter’s by a fraction e, the sampling point has moved 9.5e bit periods by then. It has to still be inside the stop bit, which is half a bit either side of where it should be: 9.5e < 0.5, so e < 5.26%. That is the whole derivation, and it is why the figure depends on the character length — a 5-bit character tolerates ±7.7% and a 9-bit one with parity ±4.3%. A real receiver does slightly worse, because it does not sample at a mathematical point: it takes three samples per bit and votes, and it can only start counting on one of its own sample ticks. Working that through for 16× sampling gives -4.64% to +4.58% on 8N1. Those are the numbers this page tests against, and they are the ones Microchip’s AVR datasheets tabulate.
Both ends spend from the same budget. The window belongs to the pair, not to either device, so the usual guidance — ±2% per device, which Microchip’s own tooling defaults to — is simply half the window with a little kept back for temperature and supply voltage. A crystal is good to ±0.01% and costs you nothing; a factory-trimmed internal RC oscillator is ±1% to ±2% over temperature and spends most of the budget on its own. That is the real reason a board with an internal-RC microcontroller talks reliably to a PC at 9600 and drops characters at 115200: not the speed, but that the divisor is smaller at 115200, so rounding it costs proportionally more.
What to do when the error is too big. Four things, in the order worth trying. Turn on double-speed or 8× oversampling, which halves the divisor and usually the rounding error with it — at the cost of some receiver tolerance. Use a part with a fractional baud generator, where the divisor is quantised to a sixteenth instead of a whole number. Change the clock: the “odd” crystals exist precisely for this, and 11.0592 MHz is exactly 115200 × 96. Or drop the baud rate, since the error shrinks as the divisor grows. What does not help is a second stop bit: only the first one is sampled.
For the timer arithmetic behind a PWM output on the same clock, see the PWM duty cycle calculator; for the crystal that feeds it, the crystal load capacitor calculator, which also gives the frequency error a wrong load capacitance causes. If the two ends run at different supply voltages, the logic level compatibility calculator checks that before the baud rate matters at all.
Frequently asked questions
What baud rate error is acceptable for UART?
About ±2% per device is the usual recommendation, and it comes from halving the receiver’s own window. For 8N1 with 16× oversampling that window is roughly −4.6% to +4.6% for the two ends together, so ±2% each leaves a margin for temperature and supply drift. Shorter characters tolerate more, longer ones less.
Why does 8 MHz not work at 115200 baud?
The exact divisor is 8,000,000 ÷ (16 × 115200) = 4.34. The hardware can only load 4, which gives 125,000 baud — 8.5% fast, well outside any receiver’s window. At 9600 the same clock wants a divisor of 52.08 and rounds to 52, an error of only 0.16%, because one count is a much smaller share of a large divisor.
What is the UART baud rate formula?
baud = f_CLK ÷ (S × divisor), where S is the oversampling ratio — 16 normally, 8 in double-speed mode. To get the divisor, compute f_CLK ÷ (S × baud) and round it. An AVR’s UBRR register holds the divisor minus one; an STM32’s USARTDIV holds it with four fractional bits.
Does double-speed mode (U2X) reduce baud rate error?
Usually yes, because the divisor doubles, so rounding it costs half as much. It is not free: sampling at 8× instead of 16× narrows the receiver’s own tolerance by about a sixth and makes it more sensitive to a noisy or slow-edged line.
Why are UART crystals odd values like 11.0592 MHz?
Because 11.0592 MHz is 115200 × 96, so every standard baud rate divides out exactly and the error is zero. The whole family — 1.8432, 3.6864, 7.3728, 14.7456, 18.432 MHz — is multiples of 1,843,200, which is 115200 × 16.
Do two stop bits make the link more tolerant?
No. The receiver samples only the first stop bit, so the arithmetic is unchanged; the second one just costs 10% of your throughput. What does change the tolerance is the number of data and parity bits, because that sets how far the sampling point has drifted by the time the stop bit arrives.
Related calculators
References
- Microchip Technology. megaAVR data sheet, USART: Asynchronous Operational Range. Defines D as the sum of data and parity bits, S as the samples per bit (16 normal, 8 double speed), and tabulates R_slow and R_fast against D with a recommended maximum receiver error. The page was reachable and those definitions and the table’s shape were confirmed, but the numeric table itself could not be extracted; the window figures on this page are computed from the relations and then checked against a tick-level simulation written for this build, which agrees with them to within the one sample tick the two derivations differ by (3.55% at worst).
- Microchip Technology. megaAVR USART configuration (Developer Help). “For baud frequency calculations, it is generally accepted that error percentages of less than ±2% are acceptable”, and the avr-libc setbaud helper defaults BAUD_TOL to ±2%.
- STMicroelectronics. AN6363, Introduction to clock requirements and calibration for STM32 MCUs. Gives the receiver budget as DTRA + DQUANT + DREC + DTCL + DWU < the USART receiver tolerance — transmitter error, baud quantisation, receiver oscillator, line and wake-up — and puts that tolerance at roughly 2% to 4% depending on character length, oversampling and sampling configuration.
- STMicroelectronics. STM32 reference manual, USART baud rate generation. baud = fCK ÷ (8 × (2 − OVER8) × USARTDIV), with USARTDIV held as a 12-bit mantissa and a 4-bit fraction — a sixteenth of a division at OVER8 = 0 and an eighth at OVER8 = 1. The manual’s own worked example, 16 MHz at 9600 baud giving USARTDIV = 104.1875 (mantissa 104, fraction 3), is reproduced exactly by this page’s arithmetic and is asserted in its test suite.