BLDC Inverter Loss Calculator — MOSFET Conduction, Switching & Thermal | CalcEngines
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BLDC Inverter Loss Calculator

Compute MOSFET conduction, switching, dead-time and reverse-recovery losses in a 3-phase inverter bridge. Compare Trapezoidal (6-step) vs Sinusoidal (FOC/SVPWM) with full junction temperature analysis.

BLDC Inverter Loss Calculator
3-phase H-bridge · MOSFET/IGBT · Thermal analysis
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Modulation Strategy
System Parameters
V
A
kHz
0–1
MOSFET / IGBT Device
mΩ
TJ >100°C correction
ns
ns
nC
ns
V
Thermal
°C/W
°C
Results
Total Inverter Loss (6 switches)
—W
—
Per MOSFET (avg)
—
IRMS per device
—
RDS effective
—
Est. Output Power
—
Conduction (I² × RDS)—
Switching (V × I × tsw)—
Dead-Time (Body diode)—
Reverse Recovery (Qrr)—
Junction Temperature TJ
—
°C
Enter parameters
2575100125155°C
3-Phase Inverter Bridge — IEC Standard Numbering (Q1–Q6)
DC+ + GND Q1 HIGH-SIDE Phase U Q4 LOW-SIDE Phase U U Q3 HIGH-SIDE Phase V Q6 LOW-SIDE Phase V V Q5 HIGH-SIDE Phase W Q2 LOW-SIDE Phase W W BLDC MOTOR U V W TRAPEZOIDAL Idle switch Active — Trap Active — Sine } Leg U
Both strategies computed from the same device parameters simultaneously. Highlighted column = currently selected mode.
Loss Comparison (per MOSFET)
Loss ComponentTrapezoidal 6-StepSinusoidal FOCDifference (Sine − Trap)
Strategy Characteristics
FeatureTrapezoidal 6-StepSinusoidal FOC/SVPWM
Active Phases2 of 3 (120° per sector)3 of 3 (continuous)
Active High-Side1 switch at a time (Q1 or Q3 or Q5)All 3 (Q1, Q3, Q5) PWM
Active Low-Side1 switch at a time (Q4 or Q6 or Q2)All 3 (Q4, Q6, Q2) PWM
IRMS per switchIpk × sqrt(1/3) ≈ 0.577 × IpkIpk / sqrt(2) ≈ 0.707 × Ipk
Switching frequency factorfsw/3 (each leg commutates 1/3 of cycle)fsw (continuous)
Torque rippleHigh — commutation bumps every 60°Near-zero with FOC
Commutation sensing3× Hall sensors (60° resolution)Encoder or sensorless observer
Control complexitySimple state machineClarke/Park transforms + PI loops
Best applicationFans, pumps, e-bikes, simple drivesServo, EV traction, CNC, robotics
Thermal Resistance Stack (Rθ Budget)
°C/W
°C/W
°C/W
Ambient Ta
25 °C
Baseline
→
Heatsink Ts
—
Rθsa = 3.5 °C/W
→
Case Tc
—
Rθcs = 0.5 °C/W
→
Junction TJ
—
Rθjc = 1.0 °C/W
Per-Device Summary — all 6 MOSFETs
SwitchRolePhasePcondPswPdiodePtotalTJ Est.
Rθ Total
—
°C/W junc→amb
Heatsink Ts
—
°C
Case Tc
—
°C
Junction TJ
—
°C
Design rule: Keep TJ < 125°C for reliable MOSFET operation. Target < 100°C for >10 year MTBF. Above 100°C, RDS(on) rises ~1.5×, creating a positive thermal feedback — RDS rises → conduction loss rises → TJ rises further.
Conduction — Trapezoidal
I_rms = I_pk × √(1/3) ≈ 0.577 × I_pk P_cond = I_rms² × Rds(on)
Each switch conducts for 120° of the 360° electrical cycle. The √(1/3) factor is the RMS of a 120° rectangular pulse normalised to a full cycle.
Conduction — Sinusoidal
I_rms = I_pk / √2 ≈ 0.707 × I_pk P_cond = I_rms² × Rds(on)
Continuous sinusoidal modulation: all three phases carry current throughout the cycle. RMS = peak/√2 for a pure sine waveform.
Switching Loss
P_sw = ½ × Vbus × I_pk × (tr + tf) × fsw × kk = 1/3 (Trapezoidal) k = 1/π (Sinusoidal)
k accounts for the fraction of the cycle during which each switch transitions at peak current. Linear in frequency — doubling fsw doubles switching loss.
Dead-Time Loss
I_avg_trap = I_pk / 3 I_avg_sine = I_pk / π P_dt = Vsd × I_avg × tdt × fsw
During each dead-band interval the body diode carries the phase current. VSD ≈ 0.7–1.0 V for Si, 2–3 V for SiC — SiC body diode losses are much higher.
Reverse Recovery
P_rr = Qrr × Vbus × fsw × kk = 1/3 (Trapezoidal) k = 1 (Sinusoidal)
Charge Qrr stored in the body diode is dissipated at turn-off. SiC MOSFETs have Qrr < 5 nC vs 50–500 nC for silicon — a major advantage at high fsw.
Junction Temperature
ΔT_sa = P_total × Rθ_sa ΔT_cs = P_fet × Rθ_cs ΔT_jc = P_fet × Rθ_jc T_J = T_amb + ΔT_sa + ΔT_cs + ΔT_jc
Each thermal resistance layer creates a temperature rise ΔT = P × Rθ. Note: heatsink rise uses total pack power; device junction uses per-device power.

3-Phase Inverter Bridge — Correct Topology Explained

A 3-phase BLDC inverter bridge consists of six power switches organised in three half-bridge legs. The correct IEC/IEEE standard numbering is: high-side switches Q1 (phase U), Q3 (phase V), Q5 (phase W) connect the positive DC bus to each phase output node. Low-side switches Q4 (phase U), Q6 (phase V), Q2 (phase W) connect each phase output node to ground. The complementary pairs are Q1/Q4, Q3/Q6, and Q5/Q2 — one pair per phase leg.

The phase output (U, V, W) is taken from the midpoint between the high-side and low-side switch of each leg. This is where the motor windings connect. Each pair is driven complementarily with a dead-time gap to prevent simultaneous conduction (shoot-through).

Common diagram error: Many online tools and textbooks incorrectly show the phase output wires crossing over each other or connecting to the wrong switch. In the correct diagram, phase U wire goes horizontally from the Q1/Q4 midpoint, phase V from Q3/Q6 midpoint, and phase W from Q5/Q2 midpoint — all at the same vertical level with no cross-overs.

MOSFET Loss Mechanisms in Motor Drives

At low switching frequencies, conduction loss (I² × RDS(on)) dominates. Since RDS(on) increases approximately 1.5–2× at 125°C, always derate in calculations. Selecting a lower RDS(on) device directly reduces conduction heating.

At high frequencies, switching loss dominates — it scales linearly with fSW. SiC MOSFETs achieve 5–10× lower switching loss than silicon equivalents, enabling operation above 100 kHz. Reverse recovery loss (Qrr) is negligible in SiC/GaN but can be significant in silicon at high voltage and frequency. Dead-time loss depends on the body diode forward voltage — much higher in SiC (2–3 V) than silicon (0.7–1 V), so adding an external Schottky diode is often worthwhile in SiC designs.

Frequently Asked Questions

What is the correct switch numbering in a 3-phase inverter?
Standard IEC/IEEE: high-side Q1 (U), Q3 (V), Q5 (W) and low-side Q4 (U), Q6 (V), Q2 (W). Complementary pairs are Q1/Q4, Q3/Q6, Q5/Q2. Each pair forms a half-bridge leg, with the phase output taken from the midpoint node between them.
Why does trapezoidal commutation have lower switching losses than sinusoidal?
In trapezoidal 6-step control, only 2 of 6 switches are actively PWM-switching at any instant (one high-side, one low-side). The effective switching frequency per leg is fSW/3. In sinusoidal FOC, all 6 switches are continuously modulated, so the effective frequency is fSW per leg — three times more switching events, producing proportionally higher switching loss.
How do I choose between SiC MOSFET and Silicon MOSFET for a motor drive?
SiC MOSFETs offer lower switching losses (enabling high fSW for better current ripple), near-zero Qrr, and higher temperature operation. The trade-off is higher cost and higher body-diode VSD (2–3 V vs 0.7–1 V for silicon), which increases dead-time losses. SiC is preferred for high-voltage (400 V+), high-frequency drives. Silicon suffices for low-voltage (< 100 V) BLDC drives where fSW < 30 kHz.
What is the maximum safe junction temperature for MOSFETs?
Most power MOSFETs are rated to TJ,max = 150–175°C. For reliable long-term operation, design to TJ < 125°C. At elevated temperature, RDS(on) rises (increasing conduction loss), threshold voltage decreases (raising shoot-through risk), and device lifetime drops exponentially per the Arrhenius relationship.
Loss models are first-order approximations for system-level design. Actual losses vary with gate drive, PCB layout parasitics, operating point, and device variation. Always validate with thermal imaging and a precision power analyser.
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